公开(公告)号：US20150093861A1

公开(公告)日：2015-04-02

申请号：US14042884

申请日：2013-10-01

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare

IPC: H01L21/84

CPC classification number: H01L21/84

Abstract: An SOI substrate includes first and second active regions separated by STI structures and including gate stacks. A spacer layer conformally deposited over the first and second regions including the gate stacks is directionally etched to define sidewall spacers along the sides of the gate stacks. An oxide layer and nitride layer are then deposited. Using a mask, the nitride layer over the first active region is removed, and the mask and oxide layer are removed to expose the SOI substrate in the first active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the first active region and a protective nitride layer is deposited. The masking, nitride layer removal, and oxide layer removal steps are then repeated to expose the SOI in the second active region. Raised source-drain structures are then epitaxially grown adjacent the gate stacks in the second active region.

Abstract translation: SOI衬底包括由STI结构分离并且包括栅叠层的第一和第二有源区。 在包括栅极堆叠的第一和第二区域上共形沉积的间隔层被定向蚀刻以沿着栅极堆叠的侧面限定侧壁间隔物。 然后沉积氧化物层和氮化物层。 使用掩模，去除第一有源区上的氮化物层，去除掩模和氧化物层以暴露第一有源区中的SOI衬底。 然后在第一有源区中与栅叠层相邻地外延生长凸起的源极 - 漏极结构，并且沉积保护性氮化物层。 然后重复掩模，氮化物层去除和氧化物层去除步骤以暴露第二有源区域中的SOI。 然后在第二活性区域中与栅叠层相邻地外延生长凸起的源极 - 漏极结构。

公开(公告)号：US20150080722A1

公开(公告)日：2015-03-19

申请号：US14548473

申请日：2014-11-20

Applicant: STMicroelectronics, Inc.

Inventor： Patrick Furlan

IPC: A61B5/00 ,  G06F19/00 ,  A61B5/02 ,  A61B5/107 ,  A61B8/08

CPC classification number: A61B5/4878 ,  A61B5/0002 ,  A61B5/0059 ,  A61B5/02 ,  A61B5/02028 ,  A61B5/103 ,  A61B5/107 ,  A61B5/1073 ,  A61B5/4528 ,  A61B5/7275 ,  A61B5/7282 ,  A61B5/742 ,  A61B8/08 ,  G01G19/44 ,  G01G23/3728 ,  G16H50/30

Abstract: A device for correlating trend data with respect to a patient's weight and lower extremity displacement can identify conditions indicative of congestive heart failure. An imaging mechanism is operable to measure lower extremity displacement over a period of time. An over-time trend analysis of both the patient's weight and the lower extremity displacement measurements is performed to determine whether over a particular sample period an increase in a patient's lower extremity displacement can be correlated with an increase in the patient's weight. When such a correlation does not exist, an alert can be issued of conditions indicative of congestive heart failure.

Abstract translation: 用于将趋势数据与患者体重和下肢位移相关联的装置可以识别指示充血性心力衰竭的条件。 成像机构可操作以在一段时间内测量下肢位移。 执行患者体重和下肢位移测量的过度时间趋势分析以确定在特定采样周期是否可以使患者的下肢位移的增加与患者体重的增加相关联。 当不存在这样的相关性时，可以发出指示充血性心力衰竭的状况的警报。

公开(公告)号：US20150071300A1

公开(公告)日：2015-03-12

申请号：US14025607

申请日：2013-09-12

Applicant: STMicroelectronics, Inc. ,  Cisco Technology, Inc.

Inventor： Gale L. SHALLOW ,  Benjamin Nelson DARBY ,  Jonathan EVANS ,  Maynard Darvel HAMMOND ,  Zhifang J. NI ,  Charaf HANNA

IPC: H04L12/823 ,  H04L12/873

CPC classification number: H04L47/323 ,  H04L45/7453 ,  H04L47/193 ,  H04N21/61 ,  H04N21/6118

Abstract: A system and method suited for improved overall data transmission having a hardware-based transceiver configured for transmitting upstream data with suppressed data packets. In TCP sessions between devices, a server seeks an “acknowledgement” that the downstream data transmission has been received by a client. Some data packets sent upstream may contain only TCP acknowledgement data and therefore may be combined with other purely TCP acknowledgement data packets in order to reduce the impact of the TCP acknowledgement packets on the overall upstream data throughput. In addition, this results in increased TCP performance in the downstream transmission direction as well because the algorithm enables replacing earlier arriving ACK packets with later arriving ACK packets which allows the device to send all TCP ACK information known to the suppressor at the earliest possible time.

Abstract translation: 一种适于改进总体数据传输的系统和方法，具有基于硬件的收发器，所述收发器被配置为用压缩的数据分组发送上行数据。 在设备之间的TCP会话中，服务器寻求客户端接收到下游数据传输的“确认”。 上游发送的一些数据包可能仅包含TCP确认数据，因此可以与其他纯TCP确认数据包组合，以减少TCP确认数据包对总体上行数据吞吐量的影响。 此外，这也导致在下游传输方向上提高的TCP性能，因为该算法能够用稍后到达的ACK分组来替换先前到达的ACK分组，这允许设备在最早的可能时间发送抑制器已知的所有TCP ACK信息。

公开(公告)号：US08970004B2

公开(公告)日：2015-03-03

申请号：US13725666

申请日：2012-12-21

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu

IPC: H01L29/00 ,  H01L27/02 ,  H01L21/266

CPC classification number: H01L27/0248 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/0255

Abstract: A junction diode array is disclosed for use in protecting integrated circuits from electrostatic discharge. The junction diodes integrate symmetric and asymmetric junction diodes of various sizes and capabilities. Some of the junction diodes are configured to provide low voltage and current discharge via un-encapsulated interconnecting wires, while others are configured to provide high voltage and current discharge via encapsulated interconnecting wires. Junction diode array elements include p-n junction diodes and N+/N++ junction diodes. The junction diodes include implanted regions having customized shapes. If both symmetric and asymmetric diodes are not needed as components of the junction diode array, the array is configured with isolation regions between diodes of either type. Some junction diode arrays include a buried oxide layer to prevent diffusion of dopants into the substrate beyond a selected depth.

Abstract translation: 公开了用于保护集成电路免受静电放电的结二极管阵列。 结二极管集成了各种尺寸和功能的对称和非对称结二极管。 一些结二极管被配置为通过未封装的互连线提供低电压和电流放电，而其它结构二极管被配置为通过封装的互连线提供高电压和电流放电。 结二极管阵列元件包括p-n结二极管和N + / N + +结二极管。 结二极管包括具有定制形状的植入区域。 如果不需要对称和非对称二极管作为结二极管阵列的组件，则阵列配置有任一类型的二极管之间的隔离区域。 一些结二极管阵列包括掩埋氧化物层，以防止掺杂剂扩散到超过选定深度的衬底中。

公开(公告)号：US20150053930A1

公开(公告)日：2015-02-26

申请号：US14464604

申请日：2014-08-20

Applicant: STMicroelectronics, Inc.

Inventor： John H. Zhang

IPC: H01L29/423 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/51 ,  C23C14/048 ,  C23C14/221 ,  H01L21/02521 ,  H01L21/02631 ,  H01L21/28088 ,  H01L21/285 ,  H01L21/2855 ,  H01L21/76831 ,  H01L21/823418 ,  H01L21/823814 ,  H01L29/456 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: Energy bands of a thin film containing molecular clusters are tuned by controlling the size and the charge of the clusters during thin film deposition. Using atomic layer deposition, an ionic cluster film is formed in the gate region of a nanometer-scale transistor to adjust the threshold voltage, and a neutral cluster film is formed in the source and drain regions to adjust contact resistance. A work function semiconductor material such as a silver bromide or a lanthanum oxide is deposited so as to include clusters of different sizes such as dimers, trimers, and tetramers, formed from isolated monomers. A type of Atomic Layer Deposition system is used to deposit on semiconductor wafers molecular clusters to form thin film junctions having selected energy gaps. A beam of ions contains different ionic clusters which are then selected for deposition by passing the beam through a filter in which different apertures select clusters based on size and orientation.

Abstract translation: 通过在薄膜沉积期间控制簇的尺寸和电荷来调节含有分子簇的薄膜的能带。 使用原子层沉积，在纳米级晶体管的栅极区域中形成离子簇膜以调节阈值电压，并且在源极和漏极区域中形成中性聚集膜以调节接触电阻。 沉积诸如溴化银或氧化镧的功函半导体材料，以便包括由分离的单体形成的不同大小的簇，例如二聚体，三聚体和四聚体。 使用一种类型的原子层沉积系统沉积在半导体晶片分子簇上以形成具有选择的能隙的薄膜结。 离子束包含不同的离子簇，然后通过使光束通过过滤器而选择沉积，其中不同孔径基于尺寸和取向选择簇。

公开(公告)号：US20150044869A1

公开(公告)日：2015-02-12

申请号：US14522011

申请日：2014-10-23

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Lindsey H. Hall ,  Michael Hatzistergos ,  Ahmet S. Ozcan ,  Fillippos Papadatos ,  Yiyi Wang

IPC: H01L21/768 ,  H01L21/3213

CPC classification number: H01L21/76877 ,  H01L21/32115 ,  H01L21/32135 ,  H01L21/76831 ,  H01L21/7684 ,  H01L21/76871 ,  H01L21/76892

Abstract: A method of forming a semiconductor device is disclosed. The method including providing a substrate with at least one insulating layer disposed thereon, the at least one insulating layer including a trench; forming at least one liner layer on the at least one insulating layer; forming a nucleation layer on the at least one liner layer; forming a first metal film on a surface of the nucleation layer; etching the first metal film; and depositing a second metal film on the etched surface of the first metal film, the second metal film substantially forming an overburden above the trench.

Abstract translation: 公开了一种形成半导体器件的方法。 所述方法包括提供其上设置有至少一个绝缘层的衬底，所述至少一个绝缘层包括沟槽; 在所述至少一个绝缘层上形成至少一个衬垫层; 在所述至少一个衬垫层上形成成核层; 在成核层的表面上形成第一金属膜; 蚀刻第一金属膜; 以及在所述第一金属膜的蚀刻表面上沉积第二金属膜，所述第二金属膜基本上在所述沟槽上形成覆盖层。

公开(公告)号：US20150044826A1

公开(公告)日：2015-02-12

申请号：US14451174

申请日：2014-08-04

Applicant: STMicroelectronics SA ,  STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Denis Rideau ,  Olivier Nier

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/78 ,  H01L21/324 ,  H01L21/762

CPC classification number: H01L29/66772 ,  H01L21/0217 ,  H01L21/324 ,  H01L21/76283 ,  H01L21/84 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/785

Abstract: The disclosure concerns a method of stressing a semiconductor layer comprising: forming, over a silicon on insulator structure having a semiconductor layer in contact with an insulating layer, one or more stressor blocks aligned with first regions of said semiconductor layer in which transistor channels are to be formed, wherein said stressor blocks are stressed such that they locally stress said semiconductor layer; and deforming second regions of said insulating layer adjacent to said first regions by temporally decreasing, by annealing, the viscosity of said insulator layer.

Abstract translation: 本公开涉及一种对半导体层施加应力的方法，包括：在绝缘体上的结构上形成绝缘体结构，该绝缘体上硅结构具有与绝缘层相接触的半导体层，一个或多个与晶体管沟道所在半导体层的第一区对准的应力块 形成，其中所述应力块被应力，使得它们局部应力所述半导体层; 以及通过退火所述绝缘体层的粘度暂时减小所述绝缘层的与所述第一区域相邻的第二区域。

公开(公告)号：US20150036543A1

公开(公告)日：2015-02-05

申请号：US14520828

申请日：2014-10-22

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS S.R.L.

Inventor： LIWEN CHU ,  GEORGE A. VLANTIS ,  VINCENZO SCARPA

IPC: H04W48/14 ,  H04W40/34 ,  H04W48/08 ,  H04W72/02

CPC classification number: H04W48/14 ,  H04W40/34 ,  H04W48/08 ,  H04W72/02 ,  H04W72/1252 ,  H04W84/12 ,  H04W84/18 ,  H04W84/22 ,  Y02D70/142 ,  Y02D70/22

Abstract: The addition of high throughput capability elements to beacon frames and peer link action frames in wireless mesh networks enable the utilization of desirable features without further modifications to the network. Rules can be established for high throughput mesh point protection in a mesh network, Space-time Block Code (STBC) operations and 20/40 MHz operation selections. However, features such as PSMP (power save multi-poll) and PCO (phased coexistence operations) are barred from implementation to prevent collisions.

Abstract translation: 在无线网状网络中向信标帧和对等链路动作帧添加高吞吐量能力元素使得能够利用所需特征而无需进一步修改网络。 可以为网格网络中的高吞吐量网格点保护，空时块代码（STBC）操作和20/40 MHz操作选择建立规则。 然而，PSMP（省电多轮询）和PCO（分阶段共存操作）等功能被禁止实施以防止冲突。

公开(公告)号：US08934390B2

公开(公告)日：2015-01-13

申请号：US13631284

申请日：2012-09-28

Applicant: STMicroelectronics, Inc.

Inventor： Liwen Chu ,  George A. Vlantis

IPC: G08C17/00 ,  G01R31/08 ,  G06F11/00 ,  G08C15/00 ,  H04J1/16 ,  H04J3/14 ,  H04L1/00 ,  H04L12/26 ,  H04L12/28 ,  H04J3/00 ,  H04L12/413

CPC classification number: H04W52/0216 ,  Y02D70/122 ,  Y02D70/142

Abstract: Enhanced low power medium access (LPMA) processes involve the enhanced LPMA STA indicating low power capabilities during association and being allocated an AID. The AID(s) for one or a group of enhanced LPMA STA(s) are included in one TIM sent during a different BEACON interval than the AID(s) for another or another group of enhanced LPMA STA(s). In addition, or alternatively, the AID(s) for enhanced LPMA STA(s) are located at an edge of the AID set within a TIM, a portion of the TIM that may be easily truncated and therefore not sent. The enhanced LPMA STAs and associated access point negotiate unique offset and sleepinterval periods for polling or data uplink by the enhanced LPMA STAs.

Abstract translation: 增强的低功率介质访问（LPMA）处理涉及增强的LPMA STA，其指示关联期间的低功率能力并且被分配AID。 一个或一组增强型LPMA STA的AID包括在与另一组或另一组增强型LPMA STA的AID不同的BEACON间隔期间发送的一个TIM中。 另外或替代地，用于增强的LPMA STA的AID位于TIM内的AID集合的边缘，该TIM的一部分可以容易地被截断，因此不被发送。 增强的LPMA STA和相关联的接入点通过增强的LPMA STA协商轮询或数据上行链路的唯一偏移和休眠间隔周期。

公开(公告)号：US20150002213A1

公开(公告)日：2015-01-01

申请号：US13931692

申请日：2013-06-28

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： John H. Zhang ,  Lawrence A. Clevenger ,  Carl Radens ,  Yiheng Xu ,  Edem Wornyo

IPC: H01L23/525 ,  H01F17/02 ,  H01L49/02

CPC classification number: H01L23/5256 ,  H01F17/0006 ,  H01F17/02 ,  H01F2017/0073 ,  H01L23/522 ,  H01L23/5227 ,  H01L23/5252 ,  H01L28/10 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Nanoscale efuses, antifuses, and planar coil inductors are disclosed. A copper damascene process can be used to make all of these circuit elements. A low-temperature copper etch process can be used to make the efuses and efuse-like inductors. The circuit elements can be designed and constructed in a modular fashion by linking a matrix of metal columns in different configurations and sizes. The number of metal columns, or the size of a dielectric mesh included in the circuit element, determines its electrical characteristics. Alternatively, the efuses and inductors can be formed from interstitial metal that is either deposited into a matrix of dielectric columns, or left behind after etching columnar openings in a block of metal. Arrays of metal columns also serve a second function as features that can improve polish uniformity in place of conventional dummy structures. Use of such modular arrays provides flexibility to integrated circuit designers.

Abstract translation: 公开了纳米级电子元件，反熔丝和平面线圈电感器。 铜镶嵌工艺可用于制造所有这些电路元件。 可以使用低温铜蚀刻工艺来制造efuse和efuse样电感器。 电路元件可以通过以不同的配置和尺寸连接金属柱的矩阵来以模块化方式设计和构造。 金属柱的数量，或包括在电路元件中的电介质网的尺寸确定其电特性。 或者，电极和电感器可以由沉积在电介质柱的基体中的间隙金属形成，或者在蚀刻金属块中的柱状开口之后留下。 金属列的阵列还具有第二功能，作为可以改善抛光均匀性以代替常规虚拟结构的特征。 使用这种模块化阵列为集成电路设计人员提供了灵活性。