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    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices
    271.
    发明申请
    Method Of Forming A Device With FINFET Split Gate Non-volatile Memory Cells And FINFET Logic Devices 有权

    公开(公告)号：US20210272973A1

    公开(公告)日：2021-09-02

    申请号：US16803876

    申请日：2020-02-27

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Feng Zhou ,  Xian Liu ,  JinHo Kim ,  Serguei Jourba ,  Catherine Decobert ,  Nhan Do

    IPC: H01L27/11534 ,  H01L27/11521

    Abstract: A method of forming a device with a silicon substrate having upwardly extending first and second fins. A first implantation forms a first source region in the first silicon fin. A second implantation forms a first drain region in the first silicon fin, and second source and drain regions in the second silicon fin. A first channel region extends between the first source and drain regions. A second channel region extends between the second source and drain regions. A first polysilicon deposition is used to form a floating gate that wraps around a first portion of the first channel region. A second polysilicon deposition is used to form an erase gate wrapping around first source region, a word line gate wrapping around a second portion of the first channel region, and a dummy gate wrapping around the second channel region. The dummy gate is replaced with a metal gate.

    Method of forming split gate memory cells
    273.
    发明授权
    Method of forming split gate memory cells 有权

    公开(公告)号：US11081553B2

    公开(公告)日：2021-08-03

    申请号：US16868143

    申请日：2020-05-06

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Leo Xing ,  Chunming Wang ,  Guo Yong Liu ,  Melvin Diao ,  Xian Liu ,  Nhan Do

    IPC: H01L21/00 ,  H01L21/28 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/423 ,  H01L21/265 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3213 ,  H01L29/788

    Abstract: A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.

    Non-volatile memory device with stored index information
    274.
    发明授权
    Non-volatile memory device with stored index information 有权

    公开(公告)号：US11074980B2

    公开(公告)日：2021-07-27

    申请号：US16813317

    申请日：2020-03-09

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Xiaozhou Qian ,  Xiao Yan Pi ,  Vipin Tiwari

    IPC: G11C16/14 ,  G11C7/10 ,  G11C16/28

    Abstract: A memory device that includes a memory array having pluralities of non-volatile memory cells, a plurality of index memory cells each associated with a different one of the pluralities of the non-volatile memory cells, and a controller. The controller is configured to erase the pluralities of non-volatile memory cells, set each of the index memory cells to a first state, and program first data into the memory array by reading the plurality of index memory cells and determining that a first one of the index memory cells is in the first state, programming the first data into the plurality of the non-volatile memory cells associated with the first one of the index memory cells, and setting the first one of the index memory cells to a second state different from the first state.

    Power line compensation for flash memory sense amplifiers
    277.
    发明授权
    Power line compensation for flash memory sense amplifiers 有权

    公开(公告)号：US11031050B2

    公开(公告)日：2021-06-08

    申请号：US16526987

    申请日：2019-07-30

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran

    IPC: G11C7/06 ,  G11C7/02 ,  G11C16/28 ,  G11C11/56 ,  G11C16/04 ,  G11C5/14 ,  G11C11/4091 ,  G11C16/30

    Abstract: In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to multilevel memory sense amplifiers. As another example, compensation can be accomplished by application of a bias voltage to the power supply. Another example is a sense amplifier configured with improved input common mode voltage range. Such sense amplifiers can be two-pair and three-pair sense amplifiers. Further examples of the invention include more simplified sense amplifier configurations, and sense amplifiers having reduced leakage current.

    Flash memory cell and associated high voltage row decoder
    279.
    发明授权
    Flash memory cell and associated high voltage row decoder 有权

    公开(公告)号：US11011240B2

    公开(公告)日：2021-05-18

    申请号：US16879663

    申请日：2020-05-20

    Applicant: Silicon Storage Technology, Inc.

    Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu

    IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/28

    Abstract: The present invention relates to a flash memory cell with only four terminals and a high voltage row decoder for operating an array of such flash memory cells. The invention allows for fewer terminals for each flash memory cell compared to the prior art, which results in a simplification of the decoder circuitry and overall die space required per flash memory cells. The invention also provides for the use of high voltages on one or more of the four terminals to allow for read, erase, and programming operations despite the lower number of terminals compared to prior art flash memory cells.

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