公开(公告)号：US5532972A

公开(公告)日：1996-07-02

申请号：US391920

申请日：1995-02-21

Applicant: Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

Inventor： Luigi Pascucci ,  Silvia Padoan ,  Carla M. Golla ,  Marco Maccarrone ,  Marco Olivo

IPC: G11C17/00 ,  G11C7/02 ,  G11C7/10 ,  G11C7/22 ,  G11C16/02 ,  G11C16/32 ,  G11C7/00

CPC classification number: G11C7/02 ,  G11C16/32 ,  G11C7/1006 ,  G11C7/22

Abstract: A circuit comprises a section generating a pulse signal for asynchronously enabling the read phases; a section generating precharge and detecting signals of adjustable duration, for controlling data reading from the memory and data supply to the output buffers; a section generating a noise suppressing signal for freezing the data in the output buffers during loading into the output circuits, and the duration of which is exactly equal to the propagation time of the data to the output circuits of the memory, as determined by propagating a data simulating signal in an output simulation circuit; a section generating a loading signal, the duration of which may be equal to that of the noise suppressing signal or extended by an extension circuit in the event the array presents slower elements which may thus be read; and a section generating a circuit reset signal.

Abstract translation: 电路包括产生用于异步地使读取相位的脉冲信号的部分; 产生预充电和检测可调节持续时间的信号的部分，用于控制从存储器读取数据并向输出缓冲器提供数据; 产生用于在加载到输出电路期间将输出缓冲器中的数据冻结的噪声抑制信号的部分，其持续时间恰好等于数据到存储器的输出电路的传播时间，如通过传播 输出仿真电路中的数据模拟信号; 产生负载信号的部分，其持续时间可以等于噪声抑制信号的延迟，或者在阵列呈现较慢的元素，由此可以被读取的情况下由扩展电路扩展; 以及产生电路复位信号的部分。

公开(公告)号：US5528683A

公开(公告)日：1996-06-18

申请号：US425228

申请日：1995-04-17

Applicant: Luciano Tomasini ,  Rinaldo Castello

Inventor： Luciano Tomasini ,  Rinaldo Castello

IPC: H03F3/343 ,  H03F3/347 ,  H03H11/48 ,  H04B1/58 ,  H04M1/58 ,  H04M1/76 ,  H04M1/00

CPC classification number: H04M1/76 ,  H04B1/586 ,  H04M1/585

Abstract: The invention relates to a method and circuit for implementing an impedance associated with a monolithically integrated telephone subscriber circuit connected to a telephone line having a pair of terminals. The circuit consists of a resistor connected serially to one terminal of the telephone line, and a series of current mirror circuits. The current mirror circuits are connected in a closed loop configuration to the one terminal of the telephone line. The current mirror circuits divide, by a predetermined factor, the value of the resistor when a DC or very low frequency signal is input to the telephone circuit.

Abstract translation: 本发明涉及一种用于实现与连接到具有一对终端的电话线的单片电话用户电路相关联的阻抗的方法和电路。 该电路包括串联连接到电话线的一个端子的电阻器和一系列电流镜电路。 电流镜电路以闭环配置连接到电话线的一个终端。 电流镜电路将DC或极低频信号输入到电话电路时以预定的因数除以电阻的值。

公开(公告)号：US5526486A

公开(公告)日：1996-06-11

申请号：US42856

申请日：1993-04-05

Applicant: David Moloney ,  Maurizio Zuffada ,  Gianfranco Vai ,  Fabrizio Sacchi

Inventor： David Moloney ,  Maurizio Zuffada ,  Gianfranco Vai ,  Fabrizio Sacchi

IPC: G06F1/24 ,  G06F7/00 ,  G06F11/00 ,  G06F11/08 ,  G06F11/28 ,  G06F11/30

CPC classification number: G06F11/0763 ,  G06F11/085 ,  G06F11/28 ,  G06F7/00

Abstract: A finite-state machine has combinatorial logic connected to a status memory which receives future state signals from the finite-state machine and sends current state signals to the finite-state machine. The combinatorial logic also receives and generates input and output signals which are external to the finite-state machine. The finite-state machine compares the future state signals to at least one reference level to set an error message to reset the finite-state machine for reliable computing and adjustment.

Abstract translation: 有限状态机具有连接到状态存储器的组合逻辑，其接收来自有限状态机的未来状态信号，并将当前状态信号发送到有限状态机。 组合逻辑还接收并产生在有限状态机外部的输入和输出信号。 有限状态机将未来状态信号与至少一个参考电平进行比较，以设置错误消息来重置有限状态机以进行可靠的计算和调整。

公开(公告)号：US5526390A

公开(公告)日：1996-06-11

申请号：US260189

申请日：1994-06-15

Applicant: Giona Fucili

Inventor： Giona Fucili

IPC: H03K21/40 ,  H03M13/00 ,  H03K23/54

CPC classification number: H03K21/40

Abstract: A decoded counter employing a shift register and a zero-detect circuit has the ability of returning to a correct state within a limited number of clock cycles if an invalid state is accidentally assumed by the counter. One of the flip-flops is provided with synchronous set while all the other flip-flops of the shift register are provided with synchronous reset. The output of the last flip-flop of the register drives a single set-reset line common to all the flip-flops and the pull-up line of the zero-detect circuit is connected to the input of the first flip-flop of the register. Optionally, one of the flip-flops may be provided with asynchronous set and the others with an asynchronous reset, for initializing the counter in a certain state through a single clear-load line.

Abstract translation: 采用移位寄存器和零检测电路的解码计数器具有在计数器意外地假设无效状态的情况下在有限数量的时钟周期内返回到正确状态的能力。 触发器中的一个提供有同步装置，而移位寄存器的所有其它触发器都具有同步复位。 寄存器的最后触发器的输出驱动所有触发器共同的单个置位复位线，零检测电路的上拉线连接到第一触发器的输入端 寄存器。 可选地，触发器中的一个可以被提供有异步集合，而其他触发器可以被提供有异步复位，用于通过单个清除负载线来在某一状态初始化计数器。

公开(公告)号：US5519775A

公开(公告)日：1996-05-21

申请号：US306243

申请日：1994-09-14

Applicant: Paolo Lagana ,  Mauro Pasetti ,  Marco Siligoni

Inventor： Paolo Lagana ,  Mauro Pasetti ,  Marco Siligoni

IPC: H04M3/18 ,  H04M19/00

CPC classification number: H04M3/18 ,  H04M19/001

Abstract: A protection device, for a telephone (or other load) 27 in series with an external protection transistor 2, includes a sensor 6 for detecting common-mode current into the load. The output of the sensor 6 is connected to affect a current source/sink combination, and imbalance in this source/sink combination produces a voltage shift which is indirectly connected to control the protection transistor.

Abstract translation: 用于与外部保护晶体管2串联的电话（或其他负载）27的保护装置包括用于检测进入负载的共模电流的传感器6。 连接传感器6的输出以影响电流源/吸收组合，并且该源/吸收组合中的不平衡产生间接连接以控制保护晶体管的电压偏移。

公开(公告)号：US5516029A

公开(公告)日：1996-05-14

申请号：US267197

申请日：1994-06-29

Applicant: Antonino Grasso ,  Antonio Pinto

Inventor： Antonino Grasso ,  Antonio Pinto

IPC: H01L21/60 ,  B23K20/00 ,  H01L21/607

CPC classification number: H01L24/85 ,  B23K20/005 ,  H01L24/78 ,  B23K2201/40 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2224/78302 ,  H01L2224/78313 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/10253

Abstract: A method for connecting a wire lead between a semiconductor circuit chip and a corresponding terminal connector of a semiconductor device includes providing a bonding tool having a working end formed with at least a pair of grooves of different length, holding one end of the wire lead to the pin of the semiconductor device in one of said grooves and bonding it, and holding the other end of said wire to the chip in the other of said grooves an bonding it. The grooves have different lengths to allow for different wire spans across the bonded connection areas, on the chip and the pins.

Abstract translation: 一种用于连接半导体电路芯片和半导体器件的相应端子连接器之间的引线的方法包括提供一种焊接工具，其具有形成有至少一对不同长度的沟槽的工作端，其将导线的一端保持在 所述半导体器件的引脚在所述凹槽中的一个中并将其接合，并且将所述导线的另一端保持在另一个所述凹槽中的芯片上，从而将其接合。 这些凹槽具有不同的长度，以允许穿过结合的连接区域，芯片和引脚上的不同的导线跨度。

公开(公告)号：US5496761A

公开(公告)日：1996-03-05

申请号：US456660

申请日：1995-06-02

Applicant: Enrico M. A. Ravanelli ,  Flavio Villa

Inventor： Enrico M. A. Ravanelli ,  Flavio Villa

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L21/761

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7801 ,  H01L29/7817

Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket--isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

Abstract translation: 集成器件包括隔离导电类型的区域，每个区域围绕具有相反导电类型的外延阱，并且容纳漏极和源极区域，并且覆盖有容纳栅极区域的氧化物层，并且在其上延伸源极，漏极和 门连接。 为了线性化外延袋隔离区域结处的电位分布并且靠近连接下方的源极区域，这些区域设置有嵌入在氧化物层中的双链冷凝器，并且其中间元件被偏置到 预定电位

公开(公告)号：US5475250A

公开(公告)日：1995-12-12

申请号：US191667

申请日：1994-02-04

Applicant: Orio Bellezza

Inventor： Orio Bellezza

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/68

CPC classification number: H01L27/11521 ,  H01L27/115 ,  Y10S257/90

Abstract: The matrix of EPROM memory cells comprises on a semiconductor substrate lines of source and drain parallel and alternated one to another, floating gate areas interposed in a checkerboard pattern between said source and drain lines and control gate lines parallel to one another and perpendicular to said source and drain lines in a superimposed condition with intermediate dielectric and aligned with respect to said floating gate areas. Field oxide areas are provided for, formed on the substrate between one and the other of said control gate lines and side fins of the floating gate areas and of the control gate lines superimposed over said field oxide areas.

Abstract translation: EPROM存储单元的矩阵包括在源极和漏极平行并交替的半导体衬底上，彼此交替布置在所述源极和漏极线之间的棋盘图案中的浮动栅极区域和彼此平行并垂直于所述源极的控制栅极线 以及具有中间电介质并且相对于所述浮动栅区对准的叠加状态的漏极线。 提供场氧化物区域，用于形成在衬底上的所述控制栅极线和浮栅区域的侧鳍之间以及叠加在所述场氧化物区域上的控制栅极线的侧鳍之间。

公开(公告)号：US5461670A

公开(公告)日：1995-10-24

申请号：US176127

申请日：1993-12-30

Applicant: Pietro Consiglio ,  Carlo Antonini ,  Gianpietro Vanalli

Inventor： Pietro Consiglio ,  Carlo Antonini ,  Gianpietro Vanalli

IPC: H04M1/00 ,  H04M1/60 ,  H04M1/738

CPC classification number: H04M1/6033 ,  H04M1/738

Abstract: A telephone subscriber system comprising a speech circuit and a ring circuit adapted to be integrated monolithically to a semiconductor material substrate and being coupled to a telephone subscriber line, respectively through first and second circuit switch of the diode bridge type, further comprises a first circuit changeover switch, under control by the user, which drives at least second and third circuit switching means connected between the first diode bridge circuit and the speech circuit. The third circuit changeover switch is connected to the speech and ring circuits at a circuit communication node which forms the system point of reference, physically coincident with the substrate. The system includes a circuit interface means for controlling the second and third circuit changeover switch by external electrical signals which are related to the circuit communication node. The circuit interface circuit comprises a diode connected with its cathode to the circuit communication node, in parallel with the third circuit changeover switch.

Abstract translation: 一种电话用户系统，包括分别通过二极管桥型的第一和第二电路开关与半导体材料基板单片集成并耦合到电话用户线路的语音电路和环形电路，还包括第一电路切换 开关，由用户控制，其驱动连接在第一二极管电桥和语音电路之间的至少第二和第三电路开关装置。 第三电路切换开关连接到形成系统参考点的电路通信节点处的语音和环形电路，与衬底物理重合。 该系统包括用于通过与电路通信节点相关的外部电信号来控制第二和第三电路转换开关的电路接口装置。 电路接口电路包括与其阴极连接到电路通信节点的二极管，与第三电路转换开关并联。

公开(公告)号：US5434445A

公开(公告)日：1995-07-18

申请号：US47965

申请日：1993-04-15

Applicant: Enrico M. A. Ravanelli ,  Flavio Villa

Inventor： Enrico M. A. Ravanelli ,  Flavio Villa

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/41 ,  H01L29/772

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/7801 ,  H01L29/7817

Abstract: An integrated device includes isolating regions of a first type of conductivity, each surrounding an epitaxial pocket of an opposite type of conductivity, and housing drain and source regions, and covered with an oxide layer housing gate regions and over which extend the source, drain and gate connections. For linearizing potential distribution at the epitaxial pocket-isolating region junction and close to the source regions beneath the connections, these regions are provided with a double chain of condensers embedded in the oxide layer and the terminal elements and the intermediate element of which are biased to predetermined potentials.

Abstract translation: 集成器件包括隔离导电类型的区域，每个区域围绕具有相反导电类型的外延阱，并且容纳漏极和源极区域，并且覆盖有容纳栅极区域的氧化物层，并且在其上延伸源极，漏极和 门连接。 为了线性化外延袋隔离区域结处的电位分布并且靠近连接下方的源极区域，这些区域设置有嵌入在氧化物层中的双链冷凝器，并且其中间元件被偏置到 预定电位。