公开(公告)号：US20080056364A1

公开(公告)日：2008-03-06

申请号：US11515473

申请日：2006-08-31

Applicant: Alexander Lyashevsky ,  Jason Yang ,  Arcot J. Preetham

Inventor： Alexander Lyashevsky ,  Jason Yang ,  Arcot J. Preetham

IPC: H04N11/04 ,  H04N11/02

CPC classification number: H04N19/85 ,  H04N19/107 ,  H04N19/172 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: Embodiments of a method and system for inter-prediction in decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps indicate which units of video data in a frame are to be processed using an inter-prediction operation. In an embodiment, inter-prediction is performed on a frame basis such that inter-prediction is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the inter-prediction such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Abstract translation: 本文描述了用于在视频数据解码中进行帧间预测的方法和系统的实施例。 在各种实施例中，高压缩率编解码器（例如H.264）是视频数据的编码方案的一部分。 实施例从编码视频数据生成的预处理控制图，以及生成包括关于解码视频数据的信息的中间控制图。 控制图指示使用帧间预测操作来处理帧中的哪个单位的视频数据。 在一个实施例中，基于帧执行帧间预测，使得在一个帧上对整个帧执行帧间预测。 在其他实施例中，交织不同帧的处理。 实施例提高了帧间预测的效率，例如允许在个人计算机或类似设备上对高压缩比编码视频数据进行解码而没有特殊的附加解码硬件。

公开(公告)号：US20080056350A1

公开(公告)日：2008-03-06

申请号：US11515311

申请日：2006-08-31

Applicant: Alexander Lyashevsky ,  Jason Yang ,  Arcot J. Preetham

Inventor： Alexander Lyashevsky ,  Jason Yang ,  Arcot J. Preetham

IPC: H04B1/66 ,  H04N11/04 ,  H04N11/02

CPC classification number: H04N19/86 ,  H04N19/436 ,  H04N19/44 ,  H04N19/61

Abstract: Embodiments of a method and system for decoding video data are described herein. In various embodiments, a high-compression-ratio codec (such as H.264) is part of the encoding scheme for the video data. Embodiments pre-process control maps that were generated from encoded video data, and generating intermediate control maps comprising information regarding decoding the video data. The control maps include information regarding rearranging the video data to be processed in parallel on multiple pipelines of a graphics processing unit (GPU) so as to optimize the use of the multiple pipelines. In an embodiment, macro blocks of video data with similar deblocking dependencies are identified to be processed together. Deblocking is performed on a frame basis such that deblocking is performed on an entire frame at one time. In other embodiments, processing of different frames is interleaved. Embodiments increase the efficiency of the decoding such as to allow decoding of high-compression-ratio encoded video data on personal computers or comparable equipment without special, additional decoding hardware.

Abstract translation: 本文描述了用于解码视频数据的方法和系统的实施例。 在各种实施例中，高压缩率编解码器（例如H.264）是视频数据的编码方案的一部分。 实施例从编码视频数据生成的预处理控制图，以及生成包括关于解码视频数据的信息的中间控制图。 控制映射包括关于在图形处理单元（GPU）的多个管线上并行处理的视频数据的重新排列的信息，以便优化多个管线的使用。 在一个实施例中，具有相似去块依赖性的视频数据的宏块被识别为一起处理。 在基于帧的基础上执行解块，使得一次在整个帧上执行解块。 在其他实施例中，交织不同帧的处理。 实施例增加了解码的效率，例如允许在个人计算机或类似设备上对高压缩比编码视频数据进行解码而没有特殊的附加解码硬件。

公开(公告)号：US20080055651A1

公开(公告)日：2008-03-06

申请号：US11468677

申请日：2006-08-30

Applicant: Jeff Wei

Inventor： Jeff Wei

IPC: G06F15/00

CPC classification number: H03M1/0641 ,  G06F7/58 ,  G06F7/584 ,  G06F2207/583 ,  H03K3/84 ,  H03M1/66 ,  H03M7/04

Abstract: A method and circuit for generating an M-bit digital dither signal with a substantially uniform probability density function and high-pass spectrum are disclosed. The circuit includes a linear feedback shift register (LFSR) with N storage elements where N>M, and a high-pass filter. The method involves sampling at least M storage elements of the LFSR with each clock cycle to form an M-bit LFSR output and high-pass filtering and the M-bit LFSR output to provide the M-bit dither signal.

Abstract translation: 公开了一种用于产生具有基本均匀的概率密度函数和高通频谱的M位数字抖动信号的方法和电路。 该电路包括具有N个存储元件（N> M）的线性反馈移位寄存器（LFSR）和高通滤波器。 该方法涉及每个时钟周期至少对LFSR的M个存储元件进行采样，以形成M位LFSR输出和高通滤波，以及M位LFSR输出以提供M位抖动信号。

公开(公告)号：US20080055321A1

公开(公告)日：2008-03-06

申请号：US11513389

申请日：2006-08-31

Applicant: Rajabali M. Koduri

Inventor： Rajabali M. Koduri

IPC: G06F15/80

CPC classification number: G06T15/005 ,  G06T13/00

Abstract: Embodiments of the present invention are directed to a method and computer program product for performing physics simulations and graphics processing on at least one graphics processor unit (GPU). Such a method for performing physics simulations and graphics processing on at least one GPU includes the following steps. First, physics simulations are executed on a first device embodied in the at least one GPU. Then, graphics are processed on a second device embodied in the at least one GPU responsive to the physics simulations executed on the first device. In an embodiment, the first device and second device are embodied on a single GPU. In another embodiment, the first device is embodied on a first GPU and the second device is embodied on a second GPU.

Abstract translation: 本发明的实施例涉及一种用于在至少一个图形处理器单元（GPU）上执行物理模拟和图形处理的方法和计算机程序产品。 用于对至少一个GPU执行物理模拟和图形处理的这种方法包括以下步骤。 首先，在体现在至少一个GPU中的第一设备上执行物理模拟。 然后，响应于在第一设备上执行的物理仿真，在包含在至少一个GPU中的第二设备上处理图形。 在一个实施例中，第一设备和第二设备被体现在单个GPU上。 在另一个实施例中，第一设备被实现在第一GPU上，并且第二设备被实现在第二GPU上。

公开(公告)号：US20080054942A1

公开(公告)日：2008-03-06

申请号：US11469311

申请日：2006-08-31

Applicant: Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

Inventor： Oleg Drapkin ,  Grigori Temkine ,  Arvind Bomdica ,  Kevin Liang

IPC: H03K19/0185

CPC classification number: H03K19/0185 ,  H03K19/094

Abstract: An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a threshold value, the first logic one reference signal generator selectively generates a first logic one reference signal. When the voltage level of the input signal is greater than or equal to the threshold value, the second logic one reference signal generator alternatively generates a second logic one reference signal. The first and second logic one reference signals may be used to control a first voltage scaling circuit that drives a scaled output signal having a logic one value corresponding to the voltage level of the first logic one reference signal.

公开(公告)号：US20080054490A1

公开(公告)日：2008-03-06

申请号：US11469194

申请日：2006-08-31

Applicant: Neil R. McLellan ,  Vincent K. Chan ,  Roden R. Topacio

Inventor： Neil R. McLellan ,  Vincent K. Chan ,  Roden R. Topacio

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L21/563 ,  H01L21/561 ,  H01L23/16 ,  H01L23/24 ,  H01L23/3128 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/26175 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83051 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present disclosure relates to an improved integrated circuit package with a encapsulant retention structure located adjacent to a packaged integrated chip on a substrate. The structure allows for the placement and retention of a larger quantity of encapsulant to seep under the packaged integrated chip. The retention wall placed on the substrate alternatively serves as substrate stiffener able to maintain mechanical properties to be used with a more desirable thinner substrate. In one embodiment, the use of openings and recesses in a stiffener layer of an integrated circuit package houses a passive electronic component to maintain mechanical properties when a thinner substrate is used. The use of either a retention wall or a stiffener allows for the manufacture of these integrated circuit package using strip, matrix, or array technology where a larger board with a plurality of integrated circuit packages is produced industrially and then cut to individual units. The use of a retention wall of a stiffener layer over an expensive substrate layer allows for the use of disposable edges around the strip including indexing holes or other holding mechanisms. What is also contemplated is a method of manufacture of a compact strip, matrix, or array comprised of a plurality of integrated circuit packages where no waste or additional cuts are needed to produce individual integrated circuit packages.

Abstract translation: 本公开涉及一种改进的集成电路封装，其具有邻近衬底上的封装集成芯片定位的密封剂保留结构。 该结构允许在封装的集成芯片下放置和保留更大量的密封剂渗入。 放置在基板上的保持壁交替地用作能够保持机械性能以与更理想的较薄基板一起使用的基板加强件。 在一个实施例中，使用集成电路封装的加强层中的开口和凹槽容纳无源电子部件，以在使用更薄的衬底时保持机械特性。 使用保留壁或加强件允许使用条带，矩阵或阵列技术来制造这些集成电路封装，其中具有多个集成电路封装的较大的板在工业上被制造然后切割成各个单元。 在昂贵的基底层上使用加强层的保持壁允许使用围绕条带的一次性边缘，包括分度孔或其它保持机构。 还可以想到的是制造由多个集成电路封装组成的紧凑型条，矩阵或阵列的方法，其中不需要浪费或额外的切割来产生单独的集成电路封装。

公开(公告)号：US07337346B2

公开(公告)日：2008-02-26

申请号：US10792938

申请日：2004-03-04

Applicant: Gregory Agostinelli

Inventor： Gregory Agostinelli

IPC: G06F1/04

CPC classification number: G11C29/023 ,  G11C29/022 ,  G11C29/028

Abstract: A method and apparatus for fine tuning a memory interface includes receiver operative to receive an input signal. The method and apparatus includes a clock counter operative to calculate a time value based upon the timed sequence determined by the reception of the input signal. The method and apparatus further includes a comparator coupled to receive an input strength indicator signal from the receiver and operative to generate a comparative strength signal based on the comparison of the input signal strength indicator signal and a reference strength signal. Furthermore, the method and apparatus includes a tuner coupled to the clock counter so the tuner receives the time value from the counter, and coupled to the comparator to receive the comparative strength signal from the comparator, whereupon the tuner then generates a tuning signal utilized for an iterative tuning process to fine tune a memory interface.

Abstract translation: 用于微调存储器接口的方法和装置包括用于接收输入信号的接收器。 所述方法和装置包括时钟计数器，用于基于由接收输入信号确定的定时序列来计算时间值。 所述方法和装置还包括比较器，其被耦合以从接收器接收输入强度指示符信号，并且用于基于输入信号强度指示符信号和参考强度信号的比较来生成比较强度信号。 此外，该方法和装置包括一个与时钟计数器相连的调谐器，因此调谐器从计数器接收时间值，并且耦合到比较器以从比较器接收比较强度信号，于是调谐器然后产生用于 一个迭代调整过程来微调存储器接口。

公开(公告)号：US07336284B2

公开(公告)日：2008-02-26

申请号：US10820580

申请日：2004-04-08

Applicant: Stephen L. Morein ,  Michael Doggett

Inventor： Stephen L. Morein ,  Michael Doggett

IPC: G06T11/40 ,  G09G5/00 ,  G09G5/36

CPC classification number: G06F12/0897 ,  G06F3/14 ,  G06T1/60 ,  G09G2360/121 ,  G09G2360/125 ,  G09G2360/126

Abstract: A memory architecture for use in a graphics processor including a main memory, a level one (L1) cache and a level two (L2) cache, coupled between the main memory and the L1 cache is disclosed. The L2 cache stores overlapping requests to the main memory before the requested information is stored in the L1 cache. In this manner, overlapping requests for previously stored information is retrieved from the faster L2 cache as opposed to the relatively slower main memory.

Abstract translation: 公开了一种用于图形处理器的存储器架构，包括主存储器，第一级（L1）高速缓存和第二层（L2）高速缓存，耦合在主存储器和L1高速缓存之间。 在将所请求的信息存储在L1高速缓存中之前，L2高速缓存将重叠请求存储到主存储器。 以这种方式，与较慢的主存储器相比，从更快的L2高速缓存中检索先前存储的信息的重叠请求。

公开(公告)号：US20080034096A1

公开(公告)日：2008-02-07

申请号：US11461674

申请日：2006-08-01

Applicant: Azzedine Tourzni ,  Sasa Marinkovic ,  Wilson Kwan ,  Mark Bapst ,  Milivoje Aleksic ,  Kevin O'Neil

Inventor： Azzedine Tourzni ,  Sasa Marinkovic ,  Wilson Kwan ,  Mark Bapst ,  Milivoje Aleksic ,  Kevin O'Neil

IPC: G09G5/08 ,  G06F15/177 ,  G06F15/16

CPC classification number: H04N5/4401 ,  H04N5/46 ,  H04N21/4113 ,  H04N21/41407 ,  H04N21/4143 ,  H04N21/43615 ,  H04N21/43637 ,  H04N21/440263

Abstract: A demodulated multimedia signal is generated based on a captured handheld multimedia signal or a captured terrestrial multimedia signal where the handheld multimedia signal is formatted for reproduction on a handheld device and the terrestrial multimedia signal is formatted for reproduction on a computer system. The demodulated multimedia signal or a decoded multimedia signal (based on the demodulated multimedia signal) is transferred to a computer system for visual and/or audible reproduction on a computer system or for transmission to another computer system. The video information associated with the transferred signal is scaled by the computer system prior to display to match the display characteristics and capabilities of the computer system. The transferred signal may correspond to multiple channels of multimedia signals thereby enabling the display of multiple multimedia signals at the same time.

Abstract translation: 基于捕获的手持多媒体信号或捕获的地面多媒体信号产生解调的多媒体信号，其中手持多媒体信号被格式化为在手持设备上再现，并且地面多媒体信号被格式化以在计算机系统上再现。 解调的多媒体信号或解码的多媒体信号（基于解调的多媒体信号）被传送到计算机系统以在计算机系统上进行视觉和/或听觉再现或传输到另一计算机系统。 与传送的信号相关联的视频信息在显示之前由计算机系统缩放以与计算机系统的显示特性和能力相匹配。 传送的信号可以对应于多个信道的多媒体信号，从而能够同时显示多个多媒体信号。

公开(公告)号：US20080016254A1

公开(公告)日：2008-01-17

申请号：US11484191

申请日：2006-07-11

Applicant: Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

Inventor： Warren F. Kruger ,  Patrick Law ,  Alexander Miretsky

IPC: G06F15/16

CPC classification number: G06F13/1657

Abstract: Embodiments of a distributed memory controller system implemented on a single integrated circuit device are described. In one embodiment, a memory controller that provides an interconnection circuit between a first plurality of memory devices to a second plurality of memory clients includes a ring bus to route at least one of the memory request and data return signals between the memory clients and the memory devices. The ring bus is configured in a ring topography that is distributed across a portion of an integrated circuit device, resulting in a reduction in the maximum wiring density at the center of memory controller. The ring bus structure also reduces the overall number of interconnections as well as the number of storage elements, thus reducing the total area used by the memory controller. The ring bus couples memory clients that are physically located within the ring topography on the integrated circuit to external memory devices through memory device interface circuits located on the integrated circuit device. The memory controller also includes deadlock avoidance mechanisms that utilize virtual channels on the ring bus for one or more defined types of bus traffic

Abstract translation: 描述了在单个集成电路设备上实现的分布式存储器控制器系统的实施例。 在一个实施例中，在第一多个存储器设备之间提供互连电路到第二多个存储器客户端的存储器控​​制器包括环形总线，用于在存储器客户机和存储器之间路由存储器请求和数据返回信号中的至少一个 设备。 环形总线被配置为分布在集成电路器件的一部分上的环形形状，导致存储器控制器中心处的最大布线密度的降低。 环形总线结构还减少了互连的总数以及存储元件的数量，从而减少了存储器控制器使用的总面积。 环形总线通过位于集成电路设备上的存储器件接口电路将物理上位于集成电路上的环形拓扑内的存储器客户端耦合到外部存储器件。 存储器控制器还包括使用环形总线上的虚拟通道用于一个或多个定义类型的总线业务的死锁避免机制