公开(公告)号：US08639912B2

公开(公告)日：2014-01-28

申请号：US12619355

申请日：2009-11-16

Applicant: Arthur John Low ,  Stephen J. Davis

Inventor： Arthur John Low ,  Stephen J. Davis

IPC: G06F15/00 ,  G06F3/00

CPC classification number: H04L67/42 ,  H04L49/90 ,  H04L49/9036 ,  H04L63/0428 ,  H04L63/0485 ,  H04L67/34 ,  H04L69/22 ,  H04L69/329

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyze the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes. The buffer controller repeatedly makes a determination of a next process until there is no next process for a packet at which time it is provided to an output port.

Abstract translation: 公开了一种用于处理数据的数据处理器和方法。 处理器具有用于接收待处理数据的数据包的输入端口。 主控制器用于分析分组并提供包括要在数据分组上执行的进程列表及其排序的报头。 主控制器被编程有与处理器的整体处理功能相关的过程相关数据。 标题附加到数据包。 具有附加标题信息的分组被存储在缓冲器中。 缓冲器控制器用于基于分组内的报头来确定存储在缓冲器内的每个分组，以处理分组的下一个处理器。 然后，控制器将该分组提供给所确定的处理器进行处理。 返回处理后的数据包，表示处理完成。 例如，可以从进程列表中删除该进程。 缓冲器控制器重复地进行下一个处理的确定，直到在其被提供给输出端口的分组没有下一个处理为止。

公开(公告)号：US08627009B2

公开(公告)日：2014-01-07

申请号：US12211159

申请日：2008-09-16

Applicant: Nagi Nassief Mekhiel

Inventor： Nagi Nassief Mekhiel

IPC: G06F12/00

CPC classification number: G06F12/0888 ,  G06F12/0215 ,  G06F12/0897

Abstract: A method and apparatus used within memory and data processing that reduces the number of references allowed in processor cache by using active rows to reject references that are less frequently used from the cache. Comparators within a memory controller are used to generate a signal indicative of a row hit or miss, which signal is then applied to one or more demultiplexers to enable or disable transfer of a memory reference to processor cache locations. The cache may be level one (L1) or level two (L2) caches including data and or instructions or some combination of L1, L2, data, and instructions.

Abstract translation: 在存储器和数据处理中使用的方法和装置，其通过使用活动行来拒绝从缓存中较少使用的引用来减少处理器高速缓存中允许的引用数量。 存储器控制器内的比较器用于产生指示行命中或未命中的信号，然后该信号被施加到一个或多个解复用器，以启用或禁止将存储器引用传送到处理器高速缓存位置。 高速缓存可以是包括数据和/或指令的一级（L1）或二级（L2）高速缓存，或者L1，L2，数据和指令的某种组合。

公开(公告)号：US08626958B2

公开(公告)日：2014-01-07

申请号：US13077168

申请日：2011-03-31

Applicant: Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

Inventor： Hong Beom Pyeon ,  HakJune Oh ,  Jin-Ki Kim ,  Shuji Sumi

IPC: G06F3/00

CPC classification number: G11C16/20 ,  G11C8/12

Abstract: A plurality of memory devices of mixed type (e.g., DRAMs, SRAMs, MRAMs and NAND-, NOR- and AND-type Flash memories) are serially interconnected. Each device has device type information on its device type. A specific device type (DT) and a device identifier (ID) contained in a serial input (SI) are fed to one device of the serial interconnection. The device determines whether the fed DT matches the DT of the device. In a case of match, a calculator included in the device performs calculation to generate an ID for another device and the fed ID is latched in a register of the device. The generated ID is transferred to another device of the serial interconnection. In a case of no match, the ID generation is skipped and no ID is generated for another device. Such a device type match determination and ID generation or skip are performed in all devices of the serial interconnection. In cases of different device types being separately provided to the interconnected devices, sequential IDs are generated in each of the different device types and also the total number of each device type are recognized. In a case of a “don't care” code is provided to the interconnected devices, sequential IDs are generated and also, the total number of the interconnected devices is recognized, regardless of the type differences.

Abstract translation: 多个混合型存储器件（例如，DRAM，SRAM，MRAM以及NAND，NOR和AND型闪存）串联连接。 每个设备都有其设备类型的设备类型信息。 包含在串行输入（SI）中的特定设备类型（DT）和设备标识符（ID）被馈送到串行互连的一个设备。 设备确定馈送的DT是否匹配设备的DT。 在匹配的情况下，包含在该设备中的计算器执行计算以生成另一设备的ID，并且将馈送的ID锁存在设备的寄存器中。 生成的ID被传送到串行互连的另一个设备。 在不匹配的情况下，跳过ID生成，并且不会为其他设备生成ID。 在串行互连的所有设备中执行这样的设备类型匹配确定和ID生成或跳过。 在将不同设备类型分别提供给互连设备的情况下，在不同设备类型中的每一种中生成顺序ID，并且还识别每种设备类型的总数。 在向互连设备提供“不关心”代码的情况下，生成顺序ID，并且还识别互连设备的总数，而不管类型差异。

公开(公告)号：US08619538B2

公开(公告)日：2013-12-31

申请号：US12912235

申请日：2010-10-26

Applicant: Yehuda Binder

Inventor： Yehuda Binder

IPC: H04L5/20 ,  H04L12/40 ,  H04L12/66 ,  H04J1/02

CPC classification number: H04L5/20 ,  H04B3/542 ,  H04L12/66 ,  H04L2012/6421 ,  H04L2012/6424 ,  H04L2012/644 ,  H04M11/062 ,  H04M11/066 ,  Y10S439/95 ,  Y10T307/297

Abstract: A device for enabling a local area network wiring structure to simultaneously carry digital data and analog telephone signals on the same transmission medium. It is particularly applicable to a network in star topology, in which remote data units (e.g. personal computers) are each connected to a hub through a cable comprising at least two pairs of conductors, providing a data communication path in each direction. Modules at each end of the cable provide a phantom path for telephony (voice band), signals between a telephone near the data set and a PBX, through both conductor pairs in a phantom circuit arrangement. All such communication paths function simultaneously and without mutual interference. The modules comprise simple and inexpensive passive circuit components.

Abstract translation: 一种用于使局域网布线结构能够在相同传输介质上携带数字数据和模拟电话信号的装置。 特别适用于星型拓扑网络，其中远程数据单元（例如，个人计算机）各自通过包括至少两对导体的电缆连接到集线器，从而在每个方向上提供数据通信路径。 电缆两端的模块通过虚拟电路布置的两个导线对提供电话（语音频带）的虚拟路径，靠近数据集的电话和PBX之间的信号。 所有这些通信路径同时工作，没有相互干扰。 这些模块包括简单而廉价的无源电路组件。

公开(公告)号：US08594110B2

公开(公告)日：2013-11-26

申请号：US12013148

申请日：2008-01-11

Applicant: Steven A. Przybylski

Inventor： Steven A. Przybylski

IPC: H04L12/28

CPC classification number: H04L12/4637 ,  G06F13/4243 ,  H01L2224/32145 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H04L12/42 ,  Y02D10/14 ,  Y02D10/151 ,  H01L2224/32225 ,  H01L2924/00012

Abstract: In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that packets arriving on the input segment are received and interpreted by all the devices in a cluster. In other embodiments, none, some or all but one slaves per cluster are asleep or otherwise disabled so that they do not input and interpret incoming packets. Regardless, in all embodiments, the slaves of a cluster cooperate, potentially under the controller's direction, to ensure that at most one of them is actively driving the output segment at any given time. The devices may be addressed through a device ID, a cluster ID, or a combination thereof. Embodiments of the invention are suited to exploit multi-chip module implementations and forms of vertical circuit stacking.

Abstract translation: 在集群中的网络拓扑结构中，并行访问从属设备组，使得环周围的等待时间与簇的数量成比例，与集成电路的数量成正比。 集群的设备共享输入和输出环段，使得到达输入段的数据包被集群中的所有设备接收和解释。 在其他实施例中，每个群集中的一个或全部除了一个从设备是睡着的或者被禁用的，使得它们不输入和解释传入的分组。 无论如何，在所有实施例中，集群的从站可能在控制器的方向下协作，以确保其中至少一个在任何给定时间主动地驱动输出段。 可以通过设备ID，集群ID或其组合来寻址设备。 本发明的实施例适用于利用多芯片模块实现和垂直电路堆叠的形式。

公开(公告)号：US08593847B2

公开(公告)日：2013-11-26

申请号：US13713320

申请日：2012-12-13

Applicant: MOSAID Technologies Incorporated

Inventor： Jin-Ki Kim

IPC: G11C5/02

CPC classification number: G11C5/063 ,  G11C5/02 ,  G11C5/06 ,  G11C16/30 ,  H01L21/50 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05573 ,  H01L2224/13025 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack that includes non-volatile memory devices is disclosed. One of the non-volatile memory devices in the stack is a master device, and the remaining memory device or devices is a slave device(s).

公开(公告)号：US08582598B2

公开(公告)日：2013-11-12

申请号：US13351874

申请日：2012-01-17

Applicant: Yehuda Binder

Inventor： Yehuda Binder

IPC: H04L12/40

CPC classification number: H04L41/0836 ,  G05B2219/21039 ,  G05B2219/25181 ,  H04L12/40 ,  H04L12/40019 ,  H04L12/403 ,  H04L12/42 ,  H04L12/66 ,  H04L49/40

Abstract: A network for carrying out control, sensing and data communications, composed of a plurality of nodes. Each node may be connected to a payload, which includes sensors, actuators and DTE's. The network is formed using a plurality of independent communication links, each based on electrically-conducting communication media composed of at least two conductors and interconnecting two nodes, in a point-to-point configuration. During network operation, nodes can be dynamically configured as either data-generating nodes, wherein data is generated and transmitted into the network, or as receiver/repeater/router nodes, wherein received data is repeated from a receiver port to all output ports.

Abstract translation: 用于执行由多个节点组成的控制，感测和数据通信的网络。 每个节点可以连接到有效载荷，其中包括传感器，执行器和DTE。 网络使用多个独立的通信链路形成，每个通信链路基于由至少两个导体组成的导电通信介质并且以点对点配置互连两个节点。 在网络操作期间，节点可以被动态地配置为数据生成节点，其中数据被生成并发送到网络，或者作为接收器/中继器/路由器节点，其中接收的数据从接收器端口重复到所有的输出端口。

公开(公告)号：US08570828B2

公开(公告)日：2013-10-29

申请号：US13008522

申请日：2011-01-18

Applicant: Hong Beom Pyeon

Inventor： Hong Beom Pyeon

IPC: G11C8/00

CPC classification number: G11C7/1015 ,  G11C7/1006 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2013/0088

Abstract: A memory system comprises a memory including a plurality of bits arranged as one or more words. Each bit in each word is capable of being programmed either to a particular logical state or to another logical state. A variable data width controller is in communication with the memory. The variable data width controller comprises an adder to determine a programming number of bits in a word to be programmed into a memory. Each bit to be programmed is in the particular logical state. A partitioning block divides the word in to two or more sub-words when the programming number exceeds a maximum number. A switch is in communication with the partitioning block. The switch sequentially provides one or more write pulses. Each write pulse enables a separate communication path between the memory and one of the word and the sub-words.

Abstract translation: 存储器系统包括存储器，该存储器包括排列成一个或多个单词的多个位。 每个单词中的每个位都能够被编程到特定的逻辑状态或另一个逻辑状态。 可变数据宽度控制器与存储器通信。 可变数据宽度控制器包括加法器，用于确定要编程到存储器中的一个字中的位的编程位数。 要编程的每个位处于特定的逻辑状态。 当编程号码超过最大数量时，划分块将字分成两个或多个子字。 开关与分区块通信。 开关依次提供一个或多个写入脉冲。 每个写入脉冲使得存储器与字和子字中的一个之间的单独通信路径成为可能。

公开(公告)号：US08558593B2

公开(公告)日：2013-10-15

申请号：US13607015

申请日：2012-09-07

Applicant: Paul W. Demone

Inventor： Paul W. Demone

IPC: H03L7/06

CPC classification number: H03L7/06 ,  H03K5/00006 ,  H03K5/15046 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/16

Abstract: A frequency multiplier circuit comprising a delay line receiving at one end thereof a reference clock for generating clock tap outputs from respective ones of a plurality of period matched delay elements; a clock combining circuit responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period.

公开(公告)号：US08558573B2

公开(公告)日：2013-10-15

申请号：US13295433

申请日：2011-11-14

Applicant: Yehuda Binder

Inventor： Yehuda Binder

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H03K19/0005 ,  H04L5/14 ,  H04L12/40032 ,  H04L25/02 ,  H04L25/0272 ,  H04L25/0298 ,  H04L27/00 ,  H04L27/0002

Abstract: A communication system having first and second states for use with a shared transmission line composed of at least two conductors and composed of first and second transmission line segments connected to each other at a single connection point. In the first state, a termination is coupled to the single connection point and is operative to at least attenuate a signal propagated between the first and second segments. In the second state, a driver is coupled to the connection point and is operative to conduct a signal over the first and second segments.

Abstract translation: 一种具有第一和第二状态的通信系统，其用于由至少两个导体组成的共享传输线，并且由在单个连接点处彼此连接的第一和第二传输线段组成。 在第一状态中，终端耦合到单个连接点，并且可操作以至少衰减在第一和第二段之间传播的信号。 在第二状态下，驱动器耦合到连接点，并且可操作以在第一和第二段上传导信号。