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    TIMES-SLICED DESIGN SEGMENTATION
    21.
    发明申请
    TIMES-SLICED DESIGN SEGMENTATION 有权
    时代精美的设计分类

    公开(公告)号：US20150163024A1

    公开(公告)日：2015-06-11

    申请号：US14099554

    申请日：2013-12-06

    Applicant: Applied Micro Circuits Corporation

    Inventor： Dimitri MAVROIDIS

    IPC: H04L5/00

    CPC classification number: H04L47/10

    Abstract: Systems and methods for multi-channel signal processing by a series of single processing core logic circuitries in time-slicing. A first logic circuitry is configured to process multiple data streams from multiple channels in a first cycle-based time-sliced schedule. A time slice in the first cycle-based time-sliced schedule comprises a predetermined number of clock cycles allocated to a corresponding data stream. A second logic circuitry is coupled to the first logic circuitry and configured to process the data streams in a first fragment-based time-sliced schedule. A time slice in the first fragment-based time-sliced schedule is determined based on a predetermined boundary associated with the data fragment and is allocated to process a data fragment of the data streams.

    Abstract translation: 通过一系列单处理核心逻辑电路在时间分片中进行多通道信号处理的系统和方法。 第一逻辑电路被配置为在基于第一周期的时间分片调度中处理来自多个信道的多个数据流。 基于第一周期的时间分片表中的时间片包括分配给相应数据流的预定数量的时钟周期。 第二逻辑电路被耦合到第一逻辑电路并且被配置为以基于片段的第一片段时间片表进行数据流的处理。 基于与数据片段相关联的预定边界来确定基于片段的第一片段时间片段中的时间片，并且被分配以处理数据流的数据片段。

    ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD
    22.
    发明申请
    ALLOCATION OF LOAD INSTRUCTION(S) TO A QUEUE BUFFER IN A PROCESSOR SYSTEM BASED ON PREDICTION OF AN INSTRUCTION PIPELINE HAZARD 有权
    基于预测指导管道危害的处理器系统中的负载指令分配给队列缓冲区

    公开(公告)号：US20150160945A1

    公开(公告)日：2015-06-11

    申请号：US14100228

    申请日：2013-12-09

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Matthew Ashcraft ,  Richard W. Thaik

    IPC: G06F9/38 ,  G06F9/30

    CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836

    Abstract: Various aspects provide for detecting ordering violations in a memory system. A system includes a prediction component and an execution component. The prediction component predicts whether a load instruction in the system is associated with an instruction pipeline hazard. The execution component allocates the load instruction to a queue buffer in the system in response to a prediction that the load instruction is not associated with the instruction pipeline hazard.

    Abstract translation: 各种方面提供用于检测存储器系统中的排序违规。 系统包括预测组件和执行组件。 预测组件预测系统中的加载指令是否与指令管道危险相关联。 执行组件响应于预测加载指令不与指令管道危险相关联地将加载指令分配给系统中的队列缓冲器。

    Fast filtering for a transceiver
    23.
    发明授权
    Fast filtering for a transceiver 有权
    快速过滤收发器

    公开(公告)号：US09025711B2

    公开(公告)日：2015-05-05

    申请号：US13965375

    申请日：2013-08-13

    Applicant: Applied Micro Circuits Corporation

    Inventor： Moshe Malkin

    IPC: H04B1/10 ,  H04L27/06 ,  G06F17/15 ,  H04B1/12 ,  H04B1/38

    CPC classification number: H03H17/0202 ,  H03H17/0213

    Abstract: Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.

    Abstract translation: 介绍了收发器快速滤波技术。 多维滤波处理器组件（MDFPC）可以执行收发器的多个数字滤波器的配置和调整。 MDFPC可以将收发器的多个单独的滤波器作为单个更大的多维滤波器来处理，并且在单个适配操作中联合更新多个滤波器，而不是在多个滤波器上执行多个适配操作。 为了便于多维滤波器适配，MDFPC可以管理与滤波器的输入相关联的相互交叉相关。 MDFPC可以通过在频域中执行多维滤波器适配来促进多维滤波器适应，其中可以针对多个频率子信道并行执行自适应。 对于每个频率子信道，MDFPC可以执行滤波器适配，其中可以为各个频率子信道生成各自的滤波器适配矩阵以执行更新以便于管理与不同频率子信道相关联的不同交叉相关。

    MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE
    25.
    发明申请
    MULTI-STAGE ADDRESS TRANSLATION FOR A COMPUTING DEVICE 审中-公开
    用于计算设备的多级地址翻译

    公开(公告)号：US20150095610A1

    公开(公告)日：2015-04-02

    申请号：US14101948

    申请日：2013-12-10

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Amos Ben-Meir

    IPC: G06F12/10

    CPC classification number: G06F12/1027 ,  G06F12/1036 ,  G06F12/1045 ,  G06F12/109 ,  G06F2212/651

    Abstract: Providing for address translation in a virtualized system environment is disclosed herein. By way of example, a memory management apparatus is provided that comprises a shared translation look-aside buffer (TLB) that includes a plurality of translation types, each supporting a plurality of page sizes, one or more processors, and a memory management controller configured to work with the one or more processors. The memory management controller includes logic configured for caching virtual address to physical address translations and intermediate physical address to physical address translations in the shared TLB, logic configured to receive a virtual address for translation from a requester, logic configured to conduct a table walk of a translation table in the shared TLB to determine a translated physical address in accordance with the virtual address, and logic configured to transmit the translated physical address to the requester.

    Abstract translation: 本文公开了在虚拟化系统环境中提供地址转换。 作为示例，提供了一种存储器管理装置，其包括共享翻译后备缓冲器（TLB），其包括多个翻译类型，每个翻译类型支持多个页面大小，一个或多个处理器和配置的存储器管理控制器 与一个或多个处理器一起工作。 存储器管理控制器包括配置用于将虚拟地址缓存到物理地址转换和中间物理地址到共享TLB中的物理地址转换的逻辑，被配置为从请求者接收用于转换的虚拟地址的逻辑，被配置为执行 在共享TLB中的转换表，以根据虚拟地址确定翻译的物理地址，以及配置为将转换的物理地址传送到请求者的逻辑。

    Managing requests to open and closed banks in a memory system
    26.
    发明授权
    Managing requests to open and closed banks in a memory system 有权
    管理存储系统中开放和关闭银行的请求

    公开(公告)号：US08990473B2

    公开(公告)日：2015-03-24

    申请号：US13644924

    申请日：2012-10-04

    Applicant: Applied Micro Circuits Corporation

    Inventor： Kjeld Svendsen

    IPC: G06F13/16

    CPC classification number: G06F13/1626 ,  G06F11/3037 ,  G06F13/1642

    Abstract: Systems and methods are provided that facilitate memory storage in a memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array writes or retrieves data contained therein based upon the command. The memory controller can monitor multiple banks and manage bank activations. Accordingly, memory access overhead can be reduced and memory devices can be more efficient.

    Abstract translation: 提供了便于存储器件中的存储器存储的系统和方法。 该系统包含存储器控制器和通信地耦合到存储器控制器的存储器阵列。 存储器控制器向存储器阵列发送命令，并且存储器阵列基于该命令写入或检索其中包含的数据。 内存控制器可以监控多个银行并管理银行激活。 因此，可以减少存储器访问开销，并且存储器设备可以更有效率。

    MAPPING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS
    28.
    发明申请
    MAPPING A PLURALITY OF SIGNALS TO GENERATE A COMBINED SIGNAL COMPRISING A HIGHER DATA RATE THAN A DATA RATE ASSOCIATED WITH THE PLURALITY OF SIGNALS 有权
    绘制大量信号以产生包含与信号多样性相关的数据速率的较高数据速率的组合信号

    公开(公告)号：US20150078406A1

    公开(公告)日：2015-03-19

    申请号：US14027518

    申请日：2013-09-16

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Francesco Caggioni ,  Dimitrios Giannakopoulos

    IPC: H04J3/16

    CPC classification number: H04J3/1664

    Abstract: Various aspects provide for mapping a plurality of signals to generate a combined signal. An aggregation component is configured for generating a combined signal that comprises a higher data rate than a data rate associated with a plurality of signals based on mapped data associated with the plurality of signals. The aggregation component comprises a mapper component. The mapper component is configured for generating the mapped data based on a mapping distribution pattern associated with a generic mapping procedure. In an aspect, a de-aggregation component is configured for recovering the plurality of signals from a pseudo signal transmitted at a data rate of the combined signal. In another aspect, the de-aggregation component comprises a de-mapper component configured for de-mapping the mapped data based on the mapping distribution pattern associated with the generic mapping procedure.

    Abstract translation: 各种方面提供用于映射多个信号以生成组合信号。 聚合组件被配置为基于与多个信号相关联的映射数据来生成包括比与多个信号相关联的数据速率更高的数据速率的组合信号。 聚合组件包括映射器组件。 映射器组件被配置用于基于与通用映射过程相关联的映射分布模式来生成映射数据。 在一方面，解聚合组件被配置为从以组合信号的数据速率发送的伪信号中恢复多个信号。 在另一方面，解聚合组件包括解映射器组件，其被配置为基于与通用映射过程相关联的映射分布模式来对映射的数据进行解映射。

    Adaptive spectral enhancement and harmonic separation
    29.
    发明授权
    Adaptive spectral enhancement and harmonic separation 有权
    自适应光谱增强和谐波分离

    公开(公告)号：US08964890B2

    公开(公告)日：2015-02-24

    申请号：US13910779

    申请日：2013-06-05

    Applicant: Applied Micro Circuits Corporation

    Inventor： Dariush Dabiri ,  Maged F. Barsoum

    IPC: H04K1/02 ,  H03H21/00

    CPC classification number: H03H21/0021 ,  H03H21/0012

    Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ω1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal φ1 (or its complement). The fundamental-enhanced signal φ1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y-φ1. The fundamental-notched signal y-φ1is itself enhanced to generate a harmonic-enhanced signal φ2 that is used to notch the fundamental-notched signal y-φ1again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ω1. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

    Abstract translation: 电路和方法在包括未知频率的电磁干扰（EMI）的输入信号y上对频率ω1（也称为“基本”频率）执行自适应频谱增强，以产生基本增强信号＆phgr; 1（或其 补充）。 1，然后在切口电路（也称为“基本陷波”电路）中使用基本增强的信号＆amp; 1（或补码）以产生基本缺口信号y-＆phgr; 1。 基本缺陷信号y-＆phgr; 1本身被增强以产生用于在串联连接的一个或多个附加凹口电路中陷入基本缺陷信号y-＆phgr; 1again的谐波增强信号＆ph2; 与基本的开槽电路。 结果（“级联谐波陷波”信号）相对没有EMI噪声（基波和谐波），并被用作自适应电路的误差信号，自适应电路进而识别基频ω1。 使用级联谐波陷波信号作为误差信号提高适应性收敛速度。

    FREQUENCY SYNTHESIS WITH GAPPER
    30.
    发明申请
    FREQUENCY SYNTHESIS WITH GAPPER 有权
    频率合成与GAPPER

    公开(公告)号：US20140266328A1

    公开(公告)日：2014-09-18

    申请号：US13846311

    申请日：2013-03-18

    Applicant: APPLIED MICRO CIRCUITS CORPORATION

    Inventor： Yehuda AZENKOT ,  Michael GROSNER ,  Timothy P. WALKER

    IPC: H03L7/16

    CPC classification number: H03L7/06

    Abstract: Systems and methods for frequency synthesis using a gapper. A frequency synthesizer may comprise a gapper, a first integer divider and a Phase Locked Loop (PLL). When a frequency of an output signal is intended to be greater than a corresponding input signal, a factor can be borrowed by the gapper from the first integer divider to generate a rational divide ratio G that is greater 1 in order for the gapper to be capable of performing the division by G. The PLL is capable of multiplying a gapped signal output from the first integer divider and attenuating jitter from the gapped signal.

    Abstract translation: 使用缝隙器进行频率合成的系统和方法。 频率合成器可以包括间隔器，第一整数除法器和锁相环（PLL）。 当输出信号的频率意图大于相应的输入信号时，由第一整数除法器可以通过间隙借用一个因子，以便产生一个大于1的有理分频比G，以使分频器能够 通过G执行除法。PLL能够将从第一整数分频器输出的有间隙信号相乘并衰减来自有间隙信号的抖动。

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