公开(公告)号：US20050272187A1

公开(公告)日：2005-12-08

申请号：US11204418

申请日：2005-08-15

Applicant: Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

Inventor： Anand Murthy ,  Brian Doyle ,  Jack Kavalieros ,  Robert Chau

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/786

CPC classification number: H01L29/41733 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78618

Abstract: The invention relates to a transistor that includes an ultra-thin body epitaxial layer that forms an embedded junction with a channel that has a length dictated by an undercut under the gate stack for the transistor. The invention also relates to a process of forming the transistor and to a system that incorporates the transistor.

Abstract translation: 本发明涉及一种晶体管，其包括超薄体外延层，该超薄体外延层与具有由晶体管的栅极堆叠下方的底切指定的沟道的沟道形成嵌入的结。 本发明还涉及一种形成晶体管的方法和涉及晶体管的系统。

公开(公告)号：US20050079660A1

公开(公告)日：2005-04-14

申请号：US10917165

申请日：2004-08-11

Applicant: Anand Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert Chau

Inventor： Anand Murthy ,  Boyan Boyanov ,  Ravindra Soman ,  Robert Chau

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/45 ,  H01L29/78 ,  H01L21/8234

CPC classification number: H01L29/66477 ,  H01L21/2254 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: Transistors are manufactured by growing germanium source and drain regions, implanting dopant impurities into the germanium, and subsequently annealing the source and drain regions so that the dopant impurities diffuse through the germanium. The process is simpler than a process wherein germanium is insitu doped with p-type or n-type impurities. The dopant impurities diffuse easily through the germanium but not easily through underlying silicon, so that an interface between the germanium and silicon acts as a diffusion barrier and ensures positioning of the dopant atoms in the regions of the device where they improve transistor performance.

Abstract translation: 晶体管通过生长锗源极和漏极区域，将掺杂杂质注入到锗中并随后对源极和漏极区域进行退火来制造，使得掺杂剂杂质扩散通过锗。 该方法比其中锗掺杂有p型或n型杂质的方法简单。 掺杂剂杂质易于通过锗扩散，但不容易通过下面的硅，使得锗和硅之间的界面充当扩散势垒，并确保掺杂剂原子在其中提高晶体管性能的区域中的位置。

公开(公告)号：US06621131B2

公开(公告)日：2003-09-16

申请号：US10002465

申请日：2001-11-01

Applicant: Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

Inventor： Anand Murthy ,  Robert S. Chau ,  Tahir Ghani ,  Kaizad R. Mistry

IPC: H01L2976

CPC classification number: H01L29/7848 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7842

Abstract: A process is described for manufacturing an improved PMOS semiconductor transistor. Recesses are etched into a layer of epitaxial silicon. Source and drain films are deposited in the recesses. The source and drain films are made of an alloy of silicon and germanium. The alloy is epitaxially deposited on the layer of silicon. The alloy thus has a lattice having the same structure as the structure of the lattice of the layer of silicon. However, due to the inclusion of the germanium, the lattice of the alloy has a larger spacing than the spacing of the lattice of the layer of silicon. The larger spacing creates a stress in a channel of the transistor between the source and drain films. The stress increases IDSAT and IDLIN of the transistor. An NMOS transistor can be manufactured in a similar manner by including carbon instead of germanium, thereby creating a tensile stress.

公开(公告)号：US06214679B1

公开(公告)日：2001-04-10

申请号：US09476393

申请日：1999-12-30

Applicant: Anand Murthy ,  Robert S. Chau

Inventor： Anand Murthy ,  Robert S. Chau

IPC: H01L21336

CPC classification number: H01L29/66636 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/28562 ,  H01L29/045 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4941 ,  H01L29/665

Abstract: A method of forming a cobalt germanosilicide film is described. According to the present invention a silicon germanium alloy is formed on a substrate. A cobalt film is then formed on the silicon germanium alloy. The substrate is then heated to a temperature of greater than 850° C. for a period of time less than 20 seconds to form a cobalt germanium silicide film.

Abstract translation: 描述形成锗硅酸钴膜的方法。 根据本发明，在基板上形成硅锗合金。 然后在硅锗合金上形成钴膜。 然后将衬底加热至大于850℃的温度一段时间少于20秒以形成锗化锗硅化物膜。

公开(公告)号：US20200211842A1

公开(公告)日：2020-07-02

申请号：US16232535

申请日：2018-12-26

Applicant: Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

Inventor： Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L27/092 ,  H01L23/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8252

Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.

公开(公告)号：US20160204256A1

公开(公告)日：2016-07-14

申请号：US14912594

申请日：2013-09-26

Applicant: Michael JACKSON ,  Anand MURTHY ,  Glenn GLASS ,  Saurabh MORARKA ,  Chandra MOHAPATRA

Inventor： Michael Jackson ,  Anand MURTHY ,  Glenn GLASS ,  Saurabh MORARKA ,  Chandra MOHAPATRA

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/32 ,  H01L29/66568 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Methods of forming a strained channel device utilizing dislocations disposed in source/drain structures are described. Those methods and structures may include forming a thin silicon germanium material in a source/drain opening of a device comprising silicon, wherein multiple dislocations are formed in the silicon germanium material. A source/drain material may be formed on the thin silicon germanium material, wherein the dislocations induce a tensile strain in a channel region of the device.

Abstract translation: 描述了利用设置在源极/漏极结构中的位错形成应变通道器件的方法。 这些方法和结构可以包括在包括硅的器件的源/漏开口中形成薄硅锗材料，其中在硅锗材料中形成多个位错。 源/漏材料可以形成在薄硅锗材料上，其中位错在器件的沟道区域中引起拉伸应变。

公开(公告)号：US20140264280A1

公开(公告)日：2014-09-18

申请号：US13996848

申请日：2013-03-15

Applicant: Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

Inventor： Seiyon Kim ,  Daniel Aubertine ,  Kelin Kuhn ,  Anand Murthy

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: A nanowire device of the present description may be produced with the incorporation of at least one underlayer etch stop formed during the fabrication of at least one nanowire transistor in order to assist in protecting source structures and/or drain structures from damage that may result from fabrication processes. The underlayer etch stop may prevent damage to the source structures andor drain the structures, when the material used in the fabrication of the source structures andor the drain structures is susceptible to being etched by the processes used in the removal of the sacrificial materials, i.e. low selectively to the source structure and/or the drain structure materials, such that potential shorting between the transistor gate electrodes and contacts formed for the source structures andor the drain structures may be prevented.

Abstract translation: 本描述的纳米线器件可以通过结合在制造至少一个纳米线晶体管期间形成的至少一个底层蚀刻停止来产生，以便有助于保护源结构和/或漏极结构免受可能由制造产生的损伤 过程。 当用于制造源结构的材料和漏极结构易于被用于去除牺牲材料的工艺被蚀刻时，底层蚀刻停止件可以防止对源结构的损坏和排出结构，即低 选择性地连接到源极结构和/或漏极结构材料，使得可以防止晶体管栅电极和为源结构形成的触点之间的电位短路以及漏极结构。

公开(公告)号：US08482043B2

公开(公告)日：2013-07-09

申请号：US12655341

申请日：2009-12-29

Applicant: Anand Murthy ,  Boyan Boyanov ,  Glenn A Glass ,  Thomas Hoffman

Inventor： Anand Murthy ,  Boyan Boyanov ,  Glenn A Glass ,  Thomas Hoffman

IPC: H01L21/00

CPC classification number: H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US08237234B2

公开(公告)日：2012-08-07

申请号：US13082305

申请日：2011-04-07

Applicant: Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

Inventor： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC: H01L21/00

CPC classification number: H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

Abstract: Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

Abstract translation: 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US20120032265A1

公开(公告)日：2012-02-09

申请号：US13020945

申请日：2011-02-04

Applicant: Danielle Simonelli ,  Anand Murthy

Inventor： Danielle Simonelli ,  Anand Murthy

IPC: H01L29/772

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/517 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of an apparatus and methods for providing a graded high germanium compound region are generally described herein. Other embodiments may be described and claimed.

Abstract translation: 本文通常描述用于提供渐变的高锗化合物区域的装置和方法的实施例。 可以描述和要求保护其他实施例。