公开(公告)号：US09329919B2

公开(公告)日：2016-05-03

申请号：US13054344

申请日：2008-07-16

申请人： Norbert Pickel ,  Axel Bahr ,  Derek Beattie ,  Andrew Birnie ,  Carl Culshaw

发明人： Norbert Pickel ,  Axel Bahr ,  Derek Beattie ,  Andrew Birnie ,  Carl Culshaw

IPC分类号： G06F11/00 ,  G06F11/07 ,  G07C5/08

CPC分类号： G06F11/0757 ,  B60R16/023 ,  G06F11/0721 ,  G06F11/0739 ,  G06F11/0772 ,  G07C5/085

摘要： A micro controller unit including an error indicator hardware module, the error indicator module being arranged to respond to event signals representative of internal and external fault and error events perturbing the micro controller unit function by registering in non-volatile memory a record of the nature of each of the events, wherein the record of the events is inaccessible to alteration.

摘要翻译： 一种包括误差指示器硬件模块的微控制器单元，所述误差指示器模块被布置为响应于代表内部和外部故障的事件信号以及扰动所述微控制器单元功能的错误事件，其通过在非易失性存储器中注册所述的性质的记录 每个事件，其中事件的记录不可更改。

公开(公告)号：US20150137841A1

公开(公告)日：2015-05-21

申请号：US14402949

申请日：2012-06-07

申请人： Manfred Thanner ,  Carl Culshaw ,  Juergen Frank ,  Michael Staudenmaier

发明人： Manfred Thanner ,  Carl Culshaw ,  Juergen Frank ,  Michael Staudenmaier

IPC分类号： G01R31/28

CPC分类号： G01R31/2856 ,  G01R31/31701 ,  G01R31/31721

摘要： A built-in self test system comprises an integrated circuit device comprising a plurality of functional units coupled to built-in self test circuitry; a low power control unit operable to switch the integrated circuit device into a low power mode and to generate a BIST wake-up signal during or before entering the low power mode; and a built-in self test control unit coupled to the built-in self test circuitry and the low power control unit and arranged to initiate a built-in self test when receiving the BIST wake-up signal.

摘要翻译： 内置自检系统包括集成电路装置，其包括耦合到内置自测电路的多个功能单元; 低功率控制单元，可操作以将集成电路设备切换到低功率模式，并在进入低功率模式期间或之前产生BIST唤醒信号; 以及耦合到内置自检电路和低功率控制单元的内置自检控制单元，并且被布置成在接收到BIST唤醒信号时发起内置自检。

公开(公告)号：US08214674B2

公开(公告)日：2012-07-03

申请号：US12446922

申请日：2007-10-22

申请人： Carl Culshaw ,  Ross A. Mitchell

发明人： Carl Culshaw ,  Ross A. Mitchell

IPC分类号： G06F1/32

CPC分类号： G06F1/28 ,  G06F11/00

摘要： Integrated circuit having a Microcontroller Unit and Methods of Operation therefore. An integrated circuit comprises a microcontroller unit with synchronous logic operably coupled to non-clocked intelligent logic. The non-clocked intelligent logic is arranged to autonomously monitor multiple events associated with an operation of the synchronous logic and, in response thereto, the non-clocked intelligent logic initiates autonomously an alternate operational mode of the microcontroller unit. A method of operating a microcontroller unit is also described.

摘要翻译： 因此，具有微控制器单元和操作方法的集成电路。 集成电路包括具有可操作地耦合到非时钟智能逻辑的同步逻辑的微控制器单元。 非时钟智能逻辑被布置成自主监视与同步逻辑的操作相关联的多个事件，并且响应于此，非时钟智能逻辑自主地启动微控制器单元的备选操作模式。 还描述了操作微控制器单元的方法。

公开(公告)号：US20110145625A1

公开(公告)日：2011-06-16

申请号：US13059246

申请日：2008-08-26

申请人： Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

发明人： Derek Beattie ,  Carl Culshaw ,  Alan Devine ,  James Andrew Collier Scobie

IPC分类号： G06F1/04

CPC分类号： G06F1/04

摘要： A clocking system, comprises a plurality of clocked data processing devices and a clock control circuit controlling a generation of a plurality of clock signals and an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices. A method for clocking a plurality of clocked data processing devices comprises controlling a generation of a plurality of clock signals and controlling an application of the clock signals to the plurality of data processing devices, allowing to clock at least one of the data processing devices while freezing all but the at least one of the data processing devices.

摘要翻译： 时钟系统包括多个时钟数据处理装置和时钟控制电路，时钟控制电路控制多个时钟信号的产生以及时钟信号到多个数据处理装置的应用，允许对数据中的至少一个进行时钟 处理设备，同时冻结所有数据处理设备中的至少一个。 一种用于计时多个时钟数据处理装置的方法包括：控制多个时钟信号的产生并控制对多个数据处理装置的时钟信号的应用，允许在冻结期间对数据处理装置中的至少一个进行计时 所有这些数据处理设备中的至少一个。

公开(公告)号：US20100241282A1

公开(公告)日：2010-09-23

申请号：US12446922

申请日：2007-10-22

申请人： Carl Culshaw ,  Ross A. Mitchell

发明人： Carl Culshaw ,  Ross A. Mitchell

IPC分类号： G06F1/32 ,  G06F1/04 ,  G06F1/26

CPC分类号： G06F1/28 ,  G06F11/00

摘要： Integrated circuit having a Microcontroller Unit and Methods of Operation therefore. An integrated circuit comprises a microcontroller unit with synchronous logic operably coupled to non-clocked intelligent logic. The non-clocked intelligent logic is arranged to autonomously monitor multiple events associated with an operation of the synchronous logic and, in response thereto, the non-clocked intelligent logic initiates autonomously an alternate operational mode of the microcontroller unit. A method of operating a microcontroller unit is also described.

摘要翻译： 因此，具有微控制器单元和操作方法的集成电路。 集成电路包括具有可操作地耦合到非时钟智能逻辑的同步逻辑的微控制器单元。 非时钟智能逻辑被布置成自主监视与同步逻辑的操作相关联的多个事件，并且响应于此，非时钟智能逻辑自主地启动微控制器单元的备选操作模式。 还描述了操作微控制器单元的方法。

公开(公告)号：US09946669B2

公开(公告)日：2018-04-17

申请号：US14766989

申请日：2013-02-12

申请人： Alistair Robertson ,  Carl Culshaw ,  Alan Devine ,  Andrei Kovalev

发明人： Alistair Robertson ,  Carl Culshaw ,  Alan Devine ,  Andrei Kovalev

IPC分类号： G06F13/00 ,  G06F13/26 ,  G06F13/24 ,  G06F13/40

CPC分类号： G06F13/26 ,  G06F13/24 ,  G06F13/4022

摘要： A method of controlling access by a master to a peripheral includes receiving an interrupt priority level from an interrupt controller associated with the peripheral, comparing the interrupt priority level with respective a pre-established interrupt access level to obtain an interrupt level comparison result, establishing whether an access condition is satisfied in dependence on the interrupt level comparison result, and if the access condition is satisfied, granting access. If the access condition is not satisfied, access is denied. Further, a circuitry is described including a master, a peripheral, and an access control circuitry including an interrupt controller associated with the peripheral. The access control circuitry is arranged to perform a method of controlling access by the master to the peripheral.

公开(公告)号：US09759765B2

公开(公告)日：2017-09-12

申请号：US14288510

申请日：2014-05-28

申请人： Alistair James Gorman ,  Carl Culshaw ,  Josef Maria Joachim Kruecken

发明人： Alistair James Gorman ,  Carl Culshaw ,  Josef Maria Joachim Kruecken

IPC分类号： G01R31/28 ,  H03K17/687 ,  G01R31/317

CPC分类号： G01R31/2856 ,  G01R31/31715 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

摘要： An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

公开(公告)号：US20160070666A1

公开(公告)日：2016-03-10

申请号：US14778115

申请日：2013-03-22

申请人： Alistair ROBERSTON ,  Carl CULSHAW ,  Alan DEVINE

发明人： ALISTAIR ROBERSTON ,  CARL CULSHAW ,  ALAN DEVINE

IPC分类号： G06F13/28 ,  G06F13/364 ,  G06F13/42

CPC分类号： G06F13/28 ,  G06F13/364 ,  G06F13/4282

摘要： A method of controlling direct memory access of a peripheral memory of a peripheral by a master is described. The method includes checking whether there is a pending request from the peripheral for a direct memory access service, establishing whether an access condition is satisfied in dependence on at least whether there is a pending request, and, if the access condition is satisfied, granting access to the master. Also, an associated device and an associated computer program product are described.

摘要翻译： 描述了由主设备控制外围设备的外围存储器的直接存储器访问的方法。 该方法包括检查外围设备是否存在用于直接存储器访问服务的未决请求，根据至少是否存在未决请求来确定访问条件是否满足，并且如果访问条件被满足，则授予访问权限 给主人。 此外，描述了相关联的设备和相关联的计算机程序产品。

公开(公告)号：US20150346274A1

公开(公告)日：2015-12-03

申请号：US14288510

申请日：2014-05-28

申请人： ALISTAIR JAMES GORMAN ,  CARL CULSHAW ,  JOSEF MARIA JOACHIM KRUECKEN

发明人： ALISTAIR JAMES GORMAN ,  CARL CULSHAW ,  JOSEF MARIA JOACHIM KRUECKEN

IPC分类号： G01R31/28 ,  H03K17/687

CPC分类号： G01R31/2856 ,  G01R31/31715 ,  H03K17/687 ,  H03K2217/0063 ,  H03K2217/0072

摘要： An I/O cell comprising a first set of driver stages comprising, each driver stage of the first set comprising a high side switch controllable to couple an I/O node of the I/O cell to a first high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a first low voltage supply node. The I/O cell further comprising a second set of driver stages, each driver stage of the second set comprising a high side switch controllable to couple the I/O node of the I/O cell to a second high voltage supply node and a low side switch controllable to couple the I/O node of the I/O cell to a second low voltage supply node. The switches of the first set of driver stages are controllable independently of the switches of the second set of driver stages.

摘要翻译： 包括第一组驱动级的I / O单元，包括：第一组的每个驱动级包括可控制以将I / O单元的I / O节点耦合到第一高电压供应节点的高侧开关，以及低 侧开关可控制以将I / O单元的I / O节点耦合到第一低电压电源节点。 所述I / O单元还包括第二组驱动级，所述第二组的每个驱动级包括可控制以将所述I / O单元的I / O节点耦合到第二高电压供应节点的高侧开关和低 侧开关可控制以将I / O单元的I / O节点耦合到第二低电压电源节点。 第一组驱动级的开关可以独立于第二组驱动级的开关来控制。

公开(公告)号：US20140298005A1

公开(公告)日：2014-10-02

申请号：US14354005

申请日：2011-11-23

申请人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

发明人： Carl Culshaw ,  Thomas Luedeke ,  Nicolas Grossier

IPC分类号： G06F9/445

CPC分类号： G06F9/442 ,  G06F1/24 ,  G06F9/44505 ,  G06F11/0721 ,  G06F11/076

摘要： A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

摘要翻译： 微处理器设备包括至少一个复位管理模块。 所述至少一个复位管理模块被布置成检测包括第一复位电平的复位事件，确定在检测到包括第一复位电平的复位事件时是否满足了至少一个复位条件，并且引起第二复位的复位 确定已经满足至少一个复位条件。