公开(公告)号：US06780776B1

公开(公告)日：2004-08-24

申请号：US10023328

申请日：2001-12-20

申请人： Wen-Jie Qi ,  John G. Pellerin ,  William G. En ,  Mark W. Michael ,  Darin A. Chan

发明人： Wen-Jie Qi ,  John G. Pellerin ,  William G. En ,  Mark W. Michael ,  Darin A. Chan

IPC分类号： H01L21302

CPC分类号： H01L29/6659 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/3185 ,  H01L29/6656

摘要： A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.

摘要翻译： 形成半导体器件的方法在衬底上提供栅电极，并在衬底和栅电极上形成多晶硅再氧化层。 氮化物层沉积在多晶硅再氧化层上并各向异性蚀刻。多晶硅再氧化层上的蚀刻停止，在栅电极上形成氮化物偏移间隔物。 使用多晶硅再氧化层作为蚀刻停止层防止在氮化物层下方的硅衬底的气蚀，同时允许形成偏移间隔物。

公开(公告)号：US6114235A

公开(公告)日：2000-09-05

申请号：US924571

申请日：1997-09-05

申请人： David K. Foote ,  Minh Van Ngo ,  Christopher F. Lyons ,  Fei Wang ,  Raymond T. Lee ,  William G. En ,  Susan H. Chen ,  Darin A. Chan

发明人： David K. Foote ,  Minh Van Ngo ,  Christopher F. Lyons ,  Fei Wang ,  Raymond T. Lee ,  William G. En ,  Susan H. Chen ,  Darin A. Chan

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/314 ,  H01L21/768 ,  H01L21/44

CPC分类号： H01L21/0276 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/3145 ,  Y10S438/945

摘要： A multipurpose cap layer serves as a bottom anti-reflective coating (BARC) during the formation of a resist mask, a hardmask during subsequent etching processes, a hardened surface during subsequent deposition and planarization processes, and optionally as a diffusion barrier to mobile ions from subsequently deposited materials.

摘要翻译： 在形成抗蚀剂掩模，后续蚀刻工艺期间的硬掩模，随后的沉积和平坦化工艺期间的硬化表面，以及任选地作为对移动离子的扩散阻挡层，多功能盖层用作底部抗反射涂层（BARC） 随后沉积材料。

公开(公告)号：US6022799A

公开(公告)日：2000-02-08

申请号：US993828

申请日：1997-12-18

申请人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

发明人： David K. Foote ,  Minh Van Ngo ,  Darin A. Chan

IPC分类号： H01L21/027 ,  H01L21/312 ,  H01L21/314 ,  H01L21/768 ,  H01L21/8247

CPC分类号： H01L21/76895 ,  H01L21/0276 ,  H01L21/3121 ,  H01L21/3145

摘要： A local interconnection to a device region in/on a substrate is formed by depositing either silicon oxynitride or silicon oxime as an etch stop layer, at a temperature of less than about 480.degree. C. to increase the hot carrier injection (HCI) lifetime of the resulting semiconductor device. A dielectric layer is then deposited over the etch stop layer and through-holes are etched exposing the etch stop layer using a first etching process. A second etching process is then conducted, which etches through the etch stop layer exposing at least one device region. The resulting through-hole is then filled with conductive material(s) to form a local interconnection.

摘要翻译： 通过在小于约480℃的温度下沉积硅氧氮化物或硅肟作为蚀刻停止层来形成与衬底中/之上的器件区域的局部互连，以增加热载流子注入（HCI）寿命 得到的半导体器件。 然后将介电层沉积在蚀刻停止层上，并且使用第一蚀刻工艺蚀刻暴露蚀刻停止层的通孔。 然后进行第二蚀刻工艺，其蚀刻通过蚀刻停止层暴露至少一个器件区域。 然后将所形成的通孔用导电材料填充以形成局部互连。

公开(公告)号：US5614446A

公开(公告)日：1997-03-25

申请号：US479873

申请日：1995-06-07

申请人： Seshadri Ramaswami ,  Darin A. Chan

发明人： Seshadri Ramaswami ,  Darin A. Chan

IPC分类号： C23C14/50 ,  H01L21/687 ,  H01L21/28

CPC分类号： H01L21/68721 ,  C23C14/50 ,  H01L21/6875 ,  H01L2223/54493

摘要： A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer. Each tab is positioned directly above a corresponding one of the topographical mark and has an area big enough to cover such mark for avoiding metal being deposited on such mark during metal deposition of the wafer. The metal deposition system comprises a depositing system for depositing a layer of a selected metal onto the wafer. The metal deposition system also includes a holding apparatus constructed in accordance with the present invention for holding the wafer during metal deposition. The processing method comprises forming an optically transparent oxide layer over the wafer which includes at least one topographical mark and providing a metallized layer over the wafer except over such mark.

摘要翻译： 一种保持装置，金属沉积系统和晶片处理方法，其通过在金属沉积期间防止金属沉积在这些标记上，在半导体晶片上保留包括那些用作对准靶的形貌标记。 当在金属沉积之前使用CMP平坦化技术时，本发明消除了使用窗口掩模和蚀刻技术来提供新形成的金属层上的形貌标记的复制的需要。 结果，可以消除由于额外的窗口掩模和蚀刻步骤引起的成本，周期时间和屈服损失。 保持装置包括用于保持具有至少一个形状标记的晶片和具有至少一个突片的夹紧环的晶片保持器。 通过保持器将晶片压靠在夹紧环上，以将晶片固定在保持器中。 每个凸片位于相应的一个地形标记的正上方，并具有足够大的面积以覆盖这种标记，以避免在晶片的金属沉积期间金属沉积在该标记上。 金属沉积系统包括用于将选定金属层沉积到晶片上的沉积系统。 金属沉积系统还包括根据本发明构造的用于在金属沉积期间保持晶片的保持装置。 该处理方法包括在晶片之上形成光学透明的氧化物层，其包括至少一个地形标记，并且在该晶片之外提供金属化层，除了该标记之外。

公开(公告)号：US5456756A

公开(公告)日：1995-10-10

申请号：US300273

申请日：1994-09-02

申请人： Seshadri Ramaswami ,  Darin A. Chan

发明人： Seshadri Ramaswami ,  Darin A. Chan

IPC分类号： C23C14/50 ,  H01L21/687 ,  C23C14/00

CPC分类号： H01L21/68721 ,  C23C14/50 ,  H01L21/6875 ,  H01L2223/54493

摘要： A holding apparatus, a metal deposition system and a wafer processing method which preserve topographical marks, including those used as alignment targets, on a semiconductor wafer by preventing metal from depositing on such marks during metal deposition. The invention eliminates the need to use window mask and etch techniques to provide replication of topographical marks on a newly formed metal layer when a CMP planarization technique is used prior to metal deposition. As a result, cost, cycle time and yield loss due to the additional window mask and etch steps can be eliminated. The holding apparatus includes a wafer retainer for retaining a wafer which has at least one topographical mark and a clamp ring with at least one tab. The wafer is pressed against the clamp ring by the retainer for securing the wafer in the retainer. Each tab is positioned directly above a corresponding one of the topographical mark and has an area big enough to cover such mark for avoiding metal being deposited on such mark during metal deposition of the wafer. The metal deposition system comprises a depositing system for depositing a layer of a selected metal onto the wafer. The metal deposition system also includes a holding apparatus constructed in accordance with the present invention for holding the wafer during metal deposition. The processing method comprises forming an optically transparent oxide layer over the wafer which includes at least one topographical mark and providing a metallized layer over the wafer except over such mark.

摘要翻译： 一种保持装置，金属沉积系统和晶片处理方法，其通过在金属沉积期间防止金属沉积在这些标记上，在半导体晶片上保留包括那些用作对准靶的形貌标记。 当在金属沉积之前使用CMP平坦化技术时，本发明消除了使用窗口掩模和蚀刻技术来提供新形成的金属层上的形貌标记的复制的需要。 结果，可以消除由于额外的窗口掩模和蚀刻步骤引起的成本，周期时间和屈服损失。 保持装置包括用于保持具有至少一个形状标记的晶片和具有至少一个突片的夹紧环的晶片保持器。 通过保持器将晶片压靠在夹紧环上，以将晶片固定在保持器中。 每个凸片位于相应的一个地形标记的正上方，并具有足够大的面积以覆盖这种标记，以避免在晶片的金属沉积期间金属沉积在该标记上。 金属沉积系统包括用于将选定金属层沉积到晶片上的沉积系统。 金属沉积系统还包括根据本发明构造的用于在金属沉积期间保持晶片的保持装置。 该处理方法包括在晶片之上形成光学透明的氧化物层，其包括至少一个地形标记，并且在该晶片之外提供金属化层，除了该标记之外。

公开(公告)号：US20090193369A1

公开(公告)日：2009-07-30

申请号：US12022860

申请日：2008-01-30

申请人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael ,  Donna Michael

发明人： Darin A. Chan ,  Yi Zou ,  Yuansheng Ma ,  Marilyn Wright ,  Mark Michael ,  Donna Michael

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/10

摘要： The present invention generates model scenarios of semiconductor chip design and uses interpolation and Monte Carlo, with random number generation inputs, techniques to iteratively assess the models for a more comprehensive and accurate assessment of design space, and evaluation under projected manufacturing conditions. This evaluation information is then incorporated into design rules in order to improve yield.

摘要翻译： 本发明生成半导体芯片设计的模型场景，并使用插值和蒙特卡罗随机数生成输入，迭代评估模型，以更全面，准确地评估设计空间，并在预计制造条件下进行评估。 然后将该评估信息并入设计规则以提高产量。

公开(公告)号：US07023059B1

公开(公告)日：2006-04-04

申请号：US10791094

申请日：2004-03-01

申请人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Jacques J. Bertrand

发明人： Darin A. Chan ,  Simon Siu-Sing Chan ,  Jeffrey P. Patton ,  Jacques J. Bertrand

IPC分类号： H01L29/94

CPC分类号： H01L29/66636 ,  H01L21/76897 ,  H01L29/665 ,  H01L29/6653

摘要： A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain regions and on the gate. Trenches are formed in the semiconductor substrate around the gate. An interlayer dielectric is deposited above the semiconductor substrate, and contacts are then formed to the silicide.

摘要翻译： 提供一种形成具有半导体衬底的集成电路的方法。 在半导体衬底上形成栅极电介质，在栅极电介质上形成栅极。 在半导体衬底中形成源极/漏极结。 在源极/漏极区域和栅极上形成硅化物。 在栅极周围的半导体衬底中形成沟槽。 在半导体衬底上沉积层间电介质，然后与硅化物形成接触。

公开(公告)号：US06566176B1

公开(公告)日：2003-05-20

申请号：US10196644

申请日：2002-07-16

申请人： Darin A. Chan

发明人： Darin A. Chan

IPC分类号： H01L2184

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L29/78609 ,  H01L29/78612 ,  H01L29/78621

摘要： A transistor device on an SOI wafer includes a metal connect that is in contact with an underside (a bottom surface) of a body of the device. A part of the metal connect is between an active semiconductor region of the device and an underlying buried insulator layer. The metal connect is also in contact with a source of the device, thereby providing some electrical coupling between the source and the body, and as a result reducing or eliminating floating body effects in the device. A method of forming the metal interconnect includes etching away part of the buried insulator layer, for example by lateral etching or isotropic etching, and filling with metal, for example by chemical vapor deposition.

公开(公告)号：US6127261A

公开(公告)日：2000-10-03

申请号：US559054

申请日：1995-11-16

申请人： Minh Van Ngo ,  Darin A. Chan

发明人： Minh Van Ngo ,  Darin A. Chan

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/316

CPC分类号： H01L21/76801 ,  H01L21/76829 ,  H01L23/5329 ,  H01L2924/0002

摘要： A method of depositing a premetal dielectric layer involves deposition of a triple premetal dielectric layer in in-situ deposition in a single fabrication tool with each subsequent layer being deposited after a previous layer with no intervening handling step. Thus, no intervening cleaning steps or other intermediate steps are performed.

摘要翻译： 沉积预金属介电层的方法包括在单一制造工具中原位沉积中沉积三重预金属介电层，其中每个后续层在先前层之后沉积，而不需要中间处理步骤。 因此，不执行介入的清洁步骤或其他中间步骤。

公开(公告)号：US6060404A

公开(公告)日：2000-05-09

申请号：US924130

申请日：1997-09-05

申请人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

发明人： Minh Van Ngo ,  Darin A. Chan ,  Sey-Ping Sun ,  Terri Kitson ,  John Caffall

IPC分类号： H01L21/314 ,  H01L21/768 ,  H01L21/72

CPC分类号： H01L21/76801 ,  H01L21/3144 ,  H01L21/76834 ,  H01L21/76895

摘要： An in-situ deposition method allows for the forming of a dielectric layer suitable for use in forming a conductive path in a semiconductor wafer. The method includes depositing a thin SiO.sub.x N.sub.y stop layer on top of a semiconductor wafer within a chemical vapor deposition (CVD) reactor chamber having a low pressure, maintaining the low pressure following the deposition of the SiO.sub.x N.sub.y stop layer, and then depositing a thick TEOS oxide dielectric layer on the SiO.sub.x N.sub.y stop layer within the CVD reactor chamber. The in-situ deposition process reduces outgassing defects that would normally form at the interface between the SiON stop layer and the TEOS oxide dielectric layer.

摘要翻译： 原位沉积方法允许形成适合用于在半导体晶片中形成导电路径的电介质层。 该方法包括在具有低压的化学气相沉积（CVD）反应器室内的半导体晶片的顶部上沉积薄的SiOxNy阻挡层，保持在沉积SiO x N y终止层之后的低压，然后沉积厚的TEOS氧化物 在CVD反应器室内的SiOxNy停止层上的介电层。 原位沉积过程减少了通常在SiON阻挡层和TEOS氧化物介电层之间的界面处形成的除气缺陷。