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    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA
    21.
    发明申请
    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA 审中-公开
    用于转换矢量数据的方法，装置和说明

    公开(公告)号：US20140019720A1

    公开(公告)日：2014-01-16

    申请号：US13762220

    申请日：2013-02-07

    Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    IPC: G06F9/30

    CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

    Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

    Partition-free multi-socket memory system architecture
    22.
    发明授权
    Partition-free multi-socket memory system architecture 有权
    无分区多插槽内存系统架构

    公开(公告)号：US08605099B2

    公开(公告)日：2013-12-10

    申请号：US12059193

    申请日：2008-03-31

    Applicant: Eric Sprangle

    Inventor： Eric Sprangle

    IPC: G06F13/00

    CPC classification number: G06T1/20 ,  G06F3/0644 ,  G06F9/30043 ,  G06F9/3867 ,  G06F9/5016

    Abstract: A technique to increase memory bandwidth for throughput applications. In one embodiment, memory bandwidth can be increased, particularly for throughput applications, without increasing interconnect trace or pin count by pipelining pages between one or more memory storage areas on half cycles of a memory access clock.

    Abstract translation: 增加吞吐量应用程序的内存带宽的技术。 在一个实施例中，特别是对于吞吐量应用而言，可以增加存储器带宽，而不会通过在存储器访问时钟的半周期上的一个或多个存储器存储区域之间流水线页面来增加互连轨迹或引脚数。

    DEVICE, SYSTEM, AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY
    25.
    发明申请
    DEVICE, SYSTEM, AND METHOD FOR USING A MASK REGISTER TO TRACK PROGRESS OF GATHERING ELEMENTS FROM MEMORY 有权
    使用掩码寄存器跟踪记忆元素进度的设备，系统和方法

    公开(公告)号：US20110264863A1

    公开(公告)日：2011-10-27

    申请号：US13175953

    申请日：2011-07-05

    Applicant: Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

    Inventor： Eric Sprangle ,  Anwar Rohillah ,  Robert Cavin ,  Tom Forsyth ,  Michael Abrash

    IPC: G06F12/08 ,  G06F9/30

    CPC classification number: G06F15/8069 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/345 ,  G06F9/383 ,  G06F12/02 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/6028

    Abstract: A device, system and method for assigning values to elements in a first register, where each data field in a first register corresponds to a data element to be written into a second register, and where for each data field in the first register, a first value may indicate that the corresponding data element has not been written into the second register and a second value indicates that the corresponding data element has been written into the second register, reading the values of each of the data fields in the first register, and for each data field in the first register having the first value, gathering the corresponding data element and writing the corresponding data element into the second register, and changing the value of the data field in the first register from the first value to the second value. Other embodiments are described and claimed.

    Abstract translation: 一种用于将值分配给第一寄存器中的元件的装置，系统和方法，其中第一寄存器中的每个数据字段对应于要写入第二寄存器的数据元素，并且对于第一寄存器中的每个数据字段， 值可以指示相应的数据元素尚未被写入第二寄存器，第二值指示对应的数据元素已被写入第二寄存器，读取第一寄存器中每个数据域的值，并且为 第一寄存器中的每个数据字段具有第一值，收集对应的数据元素并将相应的数据元素写入第二寄存器，并将第一寄存器中的数据字段的值从第一值改变为第二值。 描述和要求保护其他实施例。

    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA
    28.
    发明申请
    METHODS, APPARATUS, AND INSTRUCTIONS FOR CONVERTING VECTOR DATA 有权
    用于转换矢量数据的方法，装置和说明

    公开(公告)号：US20090172349A1

    公开(公告)日：2009-07-02

    申请号：US11964631

    申请日：2007-12-26

    Applicant: Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    Inventor： Eric Sprangle ,  Robert D. Cavin ,  Anwar Rohillah ,  Douglas M. Carmean

    IPC: G06F9/30

    CPC classification number: G06F9/30025 ,  G06F9/30036 ,  G06F9/30043

    Abstract: A computer processor includes a decoder for decoding machine instructions and an execution unit for executing those instructions. The decoder and the execution unit are capable of decoding and executing vector instructions that include one or more format conversion indicators. For instance, the processor may be capable of executing a vector-load-convert-and-write (VLoadConWr) instruction that provides for loading data from memory to a vector register. The VLoadConWr instruction may include a format conversion indicator to indicate that the data from memory should be converted from a first format to a second format before the data is loaded into the vector register. Other embodiments are described and claimed.

    Abstract translation: 计算机处理器包括用于解码机器指令的解码器和用于执行这些指令的执行单元。 解码器和执行单元能够解码和执行包括一个或多个格式转换指示符的向量指令。 例如，处理器可能能够执行矢量加载转换和写入（VLoadConWr）指令，该指令提供将数据从存储器加载到向量寄存器。 VLoadConWr指令可以包括格式转换指示符，以指示在将数据加载到向量寄存器之前，来自存储器的数据应该从第一格式转换为第二格式。 描述和要求保护其他实施例。

    Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection
    29.
    发明授权
    Speculative scheduling of instructions with source operand validity bit and rescheduling upon carried over destination operand invalid bit detection 失效
    具有源操作数有效位的指令的推测调度，以及在目的地操作数无效位检测上重新调度

    公开(公告)号：US06925550B2

    公开(公告)日：2005-08-02

    申请号：US10040223

    申请日：2002-01-02

    Applicant: Eric Sprangle ,  Michael J. Haertel ,  David J. Sager

    Inventor： Eric Sprangle ,  Michael J. Haertel ,  David J. Sager

    IPC: G06F9/38

    CPC classification number: G06F9/3861 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857

    Abstract: A method and apparatus to execute data speculative instructions in a processor comprising at least one source register, each source register comprising a bit to indicate validity of data in the at least one source register. A data validity circuit coupled to the one or more source registers to determine the validity of the data in the source registers, and to indicate the validity of the data in a destination register based upon the validity bit in the at least one source register. The processor optionally comprising a checker unit to retire those instructions from the execution unit which write valid data to the destination register, and to re-schedules those instructions for execution which write invalid data to the destination register.

    Abstract translation: 一种在包括至少一个源寄存器的处理器中执行数据推测指令的方法和装置，每个源寄存器包括用于指示所述至少一个源寄存器中的数据的有效性的位。 数据有效性电路，耦合到所述一个或多个源寄存器，以确定所述源寄存器中的数据的有效性，以及基于所述至少一个源寄存器中的有效位来指示目的地寄存器中的数据的有效性。 处理器可选地包括检查单元，以从执行单元中退出那些将有效数据写入到目的地寄存器的指令，并重新安排将无效数据写入目的地寄存器的执行指令。

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