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    Method for forming contact
    21.
    发明授权
    Method for forming contact 有权
    形成接触的方法

    公开(公告)号：US06194309B1

    公开(公告)日：2001-02-27

    申请号：US09366552

    申请日：1999-08-04

    申请人： Gyo-Young Jin

    发明人： Gyo-Young Jin

    IPC分类号： H01L21425

    CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/5226 ,  H01L27/10855 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a contact of a semiconductor device is described, in which a conductive layer pattern is electrically connected to a semiconductor substrate and an interlayer insulating film is formed on the semiconductor substrate including the conductive layer pattern. The interlayer insulating film is etched down to a top surface of the conductive layer pattern using a contact formation mask to form a contact hole. The conductive layer pattern is isotropically etched through the contact hole so as to extend the surface area of the exposed conductive layer pattern and the contact hole is filled with conductive material, forming a contact plug electrically connected to the conductive layer pattern. It is therefore possible to extend the contact area between the conductive layer pattern and a contact plug. As a result, the contact resistance is reduced.

    摘要翻译： 描述了一种用于形成半导体器件的接触的方法，其中导电层图案电连接到半导体衬底，并且在包括导电层图案的半导体衬底上形成层间绝缘膜。 使用接触形成掩模将层间绝缘膜蚀刻到导电层图案的顶表面以形成接触孔。 通过接触孔对导电层图案进行各向同性蚀刻，以便延长暴露的导电层图案的表面积，并且用导电材料填充接触孔，形成电连接到导电层图案的接触插塞。 因此可以延长导电层图案和接触插塞之间的接触面积。 结果，接触电阻降低。

    Method of fabricating transistor of DRAM semiconductor device
    24.
    发明授权
    Method of fabricating transistor of DRAM semiconductor device 有权
    制造DRAM半导体器件晶体管的方法

    公开(公告)号：US07223649B2

    公开(公告)日：2007-05-29

    申请号：US10922055

    申请日：2004-08-18

    申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L21/8242

    CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

    摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

    摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    25.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20070108516A1

    公开(公告)日：2007-05-17

    申请号：US11552359

    申请日：2006-10-24

    申请人： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

    发明人： Sung-Sam LEE ,  Yong-Tae KIM ,  Mi-Youn KIM ,  Gyo-Young JIN ,  Dae-Won HA ,  Yun-Gi KIM

    IPC分类号： H01L29/94

    CPC分类号： H01L21/823437 ,  H01L21/823481

    摘要： A semiconductor device capable of suppressing void migration is provided. The semiconductor device includes a dummy region extending in a first direction substantially perpendicular to a second direction in which a word line extends. In addition, an isolation layer pattern may not cut the dummy region in the second direction. Consequently, leaning of the dummy region and void migration are prevented. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 提供能够抑制空穴迁移的半导体器件。 半导体器件包括在基本上垂直于字线延伸的第二方向的第一方向上延伸的虚拟区域。 此外，隔离层图案可以不在第二方向上切割伪区域。 因此，防止虚拟区域的倾斜和空隙迁移。 还提供了制造半导体器件的方法。

    Double gate field effect transistor and method of manufacturing the same
    27.
    发明申请
    Double gate field effect transistor and method of manufacturing the same 失效
    双栅场效应晶体管及其制造方法

    公开(公告)号：US20050056888A1

    公开(公告)日：2005-03-17

    申请号：US10917026

    申请日：2004-08-11

    申请人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

    发明人： Jae-Man Youn ,  Dong-gun Park ,  Gyo-young Jin ,  Yoshida Makoto ,  Tai-su Park

    IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786

    CPC分类号： H01L29/7851 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66795

    摘要： Provided is a double gate field effect transistor and a method of manufacturing the same. The method of manufacturing the double gate field effect transistor comprises forming as many fins as required by etching a silicon substrate, masking the resultant product by an insulating material such as silicon nitride, forming trench regions for device isolation and STI film by using the silicon nitride mask, forming gate oxide films on both faces of the fins after removing the hard mask, and forming a gate line. As such, unnecessary channel formation under the silicon oxide film, when a voltage higher than a threshold voltage is applied to the substrate, is prevented by forming a thick silicon oxide film on the substrate on which no protruding fins are formed.

    摘要翻译： 提供双栅场效应晶体管及其制造方法。 制造双栅场效应晶体管的方法包括通过蚀刻硅衬底形成所需的散热片，通过绝缘材料如氮化硅掩蔽所得产物，通过使用氮化硅形成用于器件隔离的沟槽区域和STI膜 掩模，在除去硬掩模之后在翅片的两个表面上形成栅极氧化膜，并形成栅极线。 因此，当在没有突出的翅片形成的基板上形成厚的氧化硅膜时，通过在基板上施加高于阈值电压的电压，在氧化硅膜下形成不需要的通道。

    SEMICONDUCTOR DEVICE
    29.
    发明申请
    SEMICONDUCTOR DEVICE 有权
    半导体器件

    公开(公告)号：US20130037882A1

    公开(公告)日：2013-02-14

    申请号：US13571805

    申请日：2012-08-10

    申请人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    发明人： Ji-young Kim ,  Gyo-young Jin ,  Hyeong-sun Hong ,  Yoo-sang Hwang ,  Sung-kwan Choi ,  Hyun-woo Chung

    IPC分类号： H01L29/78

    CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L29/4236

    摘要： A semiconductor device includes a semiconductor substrate including an active region defined by a device isolation layer, a trench extending across the active region, a buried gate filling a part of the trench and including a base portion, a first extension portion, and a second extension portion extending along an inner wall of the trench, and having different heights at sides of the base portion, and a capping layer formed on the buried gate and filling the trench.

    摘要翻译： 半导体器件包括半导体衬底，其包括由器件隔离层限定的有源区，横跨有源区延伸的沟槽，填充沟槽的一部分并包括基部的掩埋栅，第一延伸部和第二延伸部 沿着沟槽的内壁延伸的部分，并且在基部的侧面具有不同的高度，以及形成在掩埋栅极上并填充沟槽的覆盖层。

    Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate
    30.
    发明授权
    Method of doping polysilicon layer that utilizes gate insulation layer to prevent diffusion of ion implanted impurities into underlying semiconductor substrate 有权
    掺杂多晶硅层的方法，其利用栅极绝缘层以防止离子注入的杂质扩散到下面的半导体衬底中

    公开(公告)号：US07833864B2

    公开(公告)日：2010-11-16

    申请号：US11738620

    申请日：2007-04-23

    申请人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    发明人： Yong-Chul Oh ,  Wook-Je Kim ,  Nak-Jin Son ,  Se-Myeong Jang ,  Gyo-Young Jin

    IPC分类号： H01L21/8234

    CPC分类号： H01L21/823878 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/518

    摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.

    摘要翻译： 实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。 一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。 此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极 地区。 实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。