公开(公告)号：US20070126486A1

公开(公告)日：2007-06-07

申请号：US11607743

申请日：2006-12-01

申请人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

发明人： Dae Woo Lee ,  Yil Suk Yang ,  Gyu Hyun Kim ,  Soon Il Yeo ,  Jong Dae Kim

IPC分类号： H03K3/00

CPC分类号： H03K3/356156 ,  H03K3/012

摘要： Provided is a multi-threshold complementary metal oxide semiconductor (MTCMOS) latch circuit including: a data inverting circuit for inverting and outputting input data under the control of a sleep control signal; a transmission gate for transferring the data signal output from the data inverting circuit under the control of a clock control signal; a signal control circuit for outputting the data signal output from the transmission gate under the control of a reset control signal and the sleep control signal; and a feedback circuit for feeding back the signal output from the signal control circuit and preserving the data in a sleep mode. The MTCMOS latch circuit can minimize power consumption caused by a leakage current due to elements scaled down to nano scale and also contribute to high-speed operation of a logic circuit by using an element having a low threshold voltage.

摘要翻译： 提供了一种多阈值互补金属氧化物半导体（MTCMOS）锁存电路，包括：数据反相电路，用于在睡眠控制信号的控制下反相输出输入数据; 传输门，用于在时钟控制信号的控制下传送从数据反相电路输出的数据信号; 信号控制电路，用于在复位控制信号和睡眠控制信号的控制下输出从传输门输出的数据信号; 以及用于反馈从信号控制电路输出的信号并且以睡眠模式保存数据的反馈电路。 MTCMOS锁存电路可以将由于按比例缩小到纳米级的元件引起的漏电流引起的功耗最小化，并且还通过使用具有低阈值电压的元件有助于逻辑电路的高速操作。

公开(公告)号：US20110284942A1

公开(公告)日：2011-11-24

申请号：US12841845

申请日：2010-07-22

申请人： Cha-Deok DONG ,  Gyu-Hyun Kim

发明人： Cha-Deok DONG ,  Gyu-Hyun Kim

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/78 ,  H01L21/743 ,  H01L27/10876 ,  H01L27/10885

摘要： A semiconductor device includes an active region having a sidewall, which has a sidewall step, a junction formed under a surface of the sidewall step, and a buried bit line configured to contact the junction.

摘要翻译： 半导体器件包括具有侧壁的有源区，其具有侧壁台阶，形成在侧壁台阶的表面下方的结以及被配置为接触接合部的掩埋位线。

公开(公告)号：US20110212611A1

公开(公告)日：2011-09-01

申请号：US13038294

申请日：2011-03-01

申请人： Gyu Hyun KIM ,  Geun Min CHOI ,  Baik CHOI, II ,  Dong Joo KIM ,  Ji Hye HAN

发明人： Gyu Hyun KIM ,  Geun Min CHOI ,  Baik CHOI, II ,  Dong Joo KIM ,  Ji Hye HAN

IPC分类号： H01L21/20

CPC分类号： H01L21/823842

摘要： Disclosed herein is a method for forming a dual gate of a semiconductor device. The method comprises the steps of forming a first polysilicon layer doped with p-type impurity ions and a second polysilicon layer doped with n-type impurity ions on a first region and a second region of a semiconductor substrate, respectively, and sequentially subjecting the surfaces of the first and second polysilicon layers to wet cleaning, drying, and dry cleaning. The wet cleaning is performed by using a sulfuric acid peroxide mixture (SPM), a buffered oxide etchant (BOE), and Standard Clean-1 (SC-1) as cleaning solutions.

摘要翻译： 本文公开了一种用于形成半导体器件的双栅极的方法。 该方法包括以下步骤：分别在半导体衬底的第一区域和第二区域上形成掺杂有p型杂质离子的第一多晶硅层和掺杂n型杂质离子的第二多晶硅层， 的第一和第二多晶硅层进行湿式清洗，干燥和干洗。 通过使用硫酸过氧化物混合物（SPM），缓冲氧化物蚀刻剂（BOE）和标准清洁-1（SC-1）作为清洁溶液进行湿清洗。

公开(公告)号：US20070264829A1

公开(公告)日：2007-11-15

申请号：US11618681

申请日：2006-12-29

申请人： Yong Soo Choi ,  Jae Gon Choi ,  Gyu Hyun Kim

发明人： Yong Soo Choi ,  Jae Gon Choi ,  Gyu Hyun Kim

IPC分类号： H01L21/461 ,  C03C15/00 ,  C09K13/06

CPC分类号： C09K3/1463 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819 ,  H01L21/7684

摘要： A chemical mechanical polishing slurry, contains an abrasive dispersed in deionized water and an organic viscosity modifier added to adjust the viscosity of the slurry to within a range of 0.5 to 3.2 cps.

摘要翻译： 化学机械抛光浆料包含分散在去离子水中的磨料和加入的有机粘度调节剂，以将浆料的粘度调节至0.5-3.2cps的范围内。

公开(公告)号：US07116255B2

公开(公告)日：2006-10-03

申请号：US11153045

申请日：2005-06-14

申请人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

发明人： Seung-Chul Lee ,  Kwi-Dong Kim ,  Gyu-Hyun Kim ,  Jong-Ki Kwon ,  Jong-Dae Kim

IPC分类号： H03M1/66

CPC分类号： H03M1/0604 ,  H03M1/1215 ,  H03M1/167 ,  H03M1/804

摘要： A multiplying digital to analog converter comprising a digital to analog converter having a plurality of capacitors coupled in parallel, applying first signals to the capacitors during a sampling period, and applying second signals to the capacitors during an amplifying period, and an amplifier including a first amplifier electrically coupled to the digital to analog converter; a second amplifier electrically coupled to the first amplifier; and a first switch electrically coupled between an input end and an output end of the second amplifier, being turned off during a sampling period, and being turned off during an amplifying period.

公开(公告)号：US07112506B2

公开(公告)日：2006-09-26

申请号：US10878747

申请日：2004-06-28

申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

IPC分类号： H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/75

摘要： Disclosed is a method for forming a capacitor of a semiconductor device. An etch stop layer, first oxide layer and second oxide layer are sequentially deposited on an insulating interlayer of a substrate. Contact holes through which portions of the etch stop layer are exposed above plugs of the insulating interlayer are formed. The contact holes are cleaned by a cleaning solution having an etching selectivity which is higher for the first oxide layer than for the second oxide layer, thereby enlarging lower portions of the contact holes. A spacer nitride layer is formed on surfaces of the contact holes and the second oxide layer. Portions of the spacer nitride layers located on the second oxide layer and above the plugs together with portions of the etch stop layer located on the plugs are removed. A double polysilicon layer is formed on the spacer nitride layer segments.

摘要翻译： 公开了一种形成半导体器件的电容器的方法。 蚀刻停止层，第一氧化物层和第二氧化物层依次沉积在基板的绝缘中间层上。 形成了绝缘中间层的插塞之上的蚀刻停止层的部分露出的接触孔。 接触孔由具有比第二氧化物层高的第一氧化物层的蚀刻选择性的清洗溶液清洁，从而扩大接触孔的下部。 在接触孔和第二氧化物层的表面上形成间隔氮化物层。 去除位于第二氧化物层上和插塞上方的间隔氮化物层的一部分以及位于插塞上的蚀刻停止层的部分。 在间隔氮化物层段上形成双重多晶硅层。

公开(公告)号：US06893914B2

公开(公告)日：2005-05-17

申请号：US10603895

申请日：2003-06-25

申请人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

发明人： Gyu Hyun Kim ,  Hyo Geun Yoon ,  Geun Min Choi

IPC分类号： H01L21/308 ,  H01L21/304 ,  H01L21/306 ,  H01L21/311 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10894 ,  H01L21/31133 ,  H01L21/3165 ,  H01L27/10814

摘要： A method for manufacturing a semiconductor device wherein a cylindrical capacitor is formed by selectively etching an oxide film in a cell area for preventing bridging between cells during a wet etching process of the oxide film in the cell area is described herein. A step difference between the interlayer insulating film formed in the cell area and the interlayer insulating film formed in the peripheral circuit area is minimized by covering the peripheral circuit area by the photoresist film and selectively etching the oxide film in the cell area to form a cylindrical capacitor, thereby simplifying the manufacturing process. In addition, bridging between the cells is prevented by performing a simple wet etching process using a single wet station, without performing a separate dry etching process for removing the oxide film and the photoresist film pattern, thereby improving the yield of the device.

摘要翻译： 这里描述了一种用于制造半导体器件的方法，其中通过在电池区域中的氧化膜的湿蚀刻工艺中选择性地蚀刻在电池区中用于防止电池之间的桥接的氧化膜形成圆柱形电容器。 通过用光致抗蚀剂膜覆盖外围电路区域并选择性地蚀刻电池区域中的氧化膜，使形成在电池区域中的层间绝缘膜与形成在外围电路区域中的层间绝缘膜之间的阶梯差被最小化，以形成圆柱形 电容器，从而简化制造过程。 此外，通过使用单个湿站进行简单的湿式蚀刻处理来防止电池之间的桥接，而不进行用于去除氧化膜和光致抗蚀剂膜图案的单独的干蚀刻工艺，从而提高器件的产量。