公开(公告)号：US20140010021A1

公开(公告)日：2014-01-09

申请号：US14023787

申请日：2013-09-11

申请人： Ji-Sang LEE ,  Kihwan CHOI

发明人： Ji-Sang LEE ,  Kihwan CHOI

IPC分类号： G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.

摘要翻译： 在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。 第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。 该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。 如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

公开(公告)号：US20120239861A1

公开(公告)日：2012-09-20

申请号：US13337695

申请日：2011-12-27

申请人： Ji-Sang Lee ,  Joonsuc Jang ,  Sang-Hyun Joo

发明人： Ji-Sang Lee ,  Joonsuc Jang ,  Sang-Hyun Joo

IPC分类号： G06F12/00

CPC分类号： G11C11/5642 ,  G11C11/5628 ,  G11C16/0483 ,  G11C2211/5646

摘要： A method programming multi-bit data to multi-level non-volatile memory cells (MLC) includes; programming a first page of data to the MLC, programming a first page flag to an initial first flag state in response in the programming of the first page, programming a second page of data to the MLC, in response to programming the second page, determining whether the first page has been programmed and if the first page has been programmed, programming the first page flag to a final first flag state different from the initial first flag state in response to programming of the second page, and if the first page has not been programmed, inhibiting programming of the first page flag during programming of the second page.

摘要翻译： 一种将多位数据编程到多级非易失性存储单元（MLC）的方法包括： 将第一页数据编程到MLC，响应于第二页的编程，响应于第一页的编程，将第一页数据编程到MLC，将第一页标志编程为初始第一标志状态，将第二页数据编程到MLC;确定 无论第一页是否已经被编程，并且如果第一页被编程，则响应于第二页的编程，将第一页标志编程为与初始第一标记状态不同的最后的第一标记状态，并且如果第一页没有 被编程，禁止在第二页的编程期间编程第一页标志。

公开(公告)号：US20170133096A1

公开(公告)日：2017-05-11

申请号：US15274071

申请日：2016-09-23

申请人： Pil Seon Yoo ,  Ji-Sang Lee ,  Gyosoo Choo

发明人： Pil Seon Yoo ,  Ji-Sang Lee ,  Gyosoo Choo

IPC分类号： G11C16/24 ,  G11C16/30 ,  G11C16/32 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/24 ,  G11C7/04 ,  G11C16/28 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3418 ,  G11C16/3459

摘要： A nonvolatile memory device includes a memory cell, a bit line, a page buffer, and a control logic. The page buffer is connected to the memory cell through the bit line and the page buffer is configured to precharge the bit line to perform a desired operation. The desired operation may be one of a read operation and a verify operation. The control logic is configured to control bit line development time differently according to a temperature after precharging the bit line during the desired operation. The control logic is configured to determine the bit line development time according to a period of a reference clock signal that includes a different frequency depending on the temperature and/or a temperature compensation pulse signal including a pulse width that varies based on the temperature.

公开(公告)号：US20160071581A1

公开(公告)日：2016-03-10

申请号：US14674005

申请日：2015-03-31

申请人： JI-SANG LEE

发明人： JI-SANG LEE

IPC分类号： G11C11/56

CPC分类号： G11C11/5671 ,  G11C11/5628 ,  G11C16/3459 ,  G11C2211/5621

摘要： In a program operation a plurality of memory cells are programmed depending on data stored in first and second data latches. Verification read operations are performed for the plurality of memory cells using different verification voltages respectively corresponding to different program states and collecting verification read results of the verification read operations. The first data latches and the second data latches are updated depending on the collected verification read results.

摘要翻译： 在程序操作中，根据存储在第一和第二数据锁存器中的数据对多个存储器单元进行编程。 使用分别对应于不同程序状态的不同验证电压并且收集验证读取操作的验证读取结果，对多个存储器单元执行验证读取操作。 根据收集的验证读取结果，第一个数据锁存器和第二个数据锁存器被更新。

公开(公告)号：US08717822B2

公开(公告)日：2014-05-06

申请号：US14023787

申请日：2013-09-11

申请人： Ji-Sang Lee ,  Kihwan Choi

发明人： Ji-Sang Lee ,  Kihwan Choi

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.

摘要翻译： 在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。 第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。 该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。 如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。

公开(公告)号：US20110179322A1

公开(公告)日：2011-07-21

申请号：US12975476

申请日：2010-12-22

申请人： Ji-Sang LEE ,  Oh-Suk KWON

发明人： Ji-Sang LEE ,  Oh-Suk KWON

IPC分类号： G06F11/267 ,  G11C16/04 ,  G11C16/34 ,  G11C29/42

CPC分类号： G11C16/3459 ,  G06F11/1048 ,  G11C16/3454 ,  G11C2029/0411

摘要： A program verification circuit comprises a failed state counting unit and a failed bit counting unit. The failed state counting unit counts failed program states among a plurality of program states, and generates a first program mode signal indicating whether counting of failed bits is required. The failed bit counting unit selectively counts failed bits in response to the first program mode signal, and generates a second program mode signal indicating whether a program operation is completed.

摘要翻译： 程序验证电路包括故障状态计数单元和故障比特计数单元。 故障状态计数单元计数多个程序状态中的程序状态失败，并且产生指示是否需要对故障位进行计数的第一程序模式信号。 故障位计数单元响应于第一编程模式信号有选择地计数故障位，并产生指示程序操作是否完成的第二程序模式信号。

公开(公告)号：US20100232228A1

公开(公告)日：2010-09-16

申请号：US12715692

申请日：2010-03-02

申请人： Hong Soo JEON ,  Ji-Sang LEE ,  Oh Suk KWON

发明人： Hong Soo JEON ,  Ji-Sang LEE ,  Oh Suk KWON

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3454

摘要： A method of programming a memory device includes comparing a first verify voltage and a distribution voltage of at least one memory cell, and if a result of the comparison is a pass, adjusting the distribution voltage until the distribution voltage is higher than a second verify voltage while comparing the distribution voltage and the second verify voltage.

摘要翻译： 一种对存储器件进行编程的方法包括比较第一验证电压和至少一个存储器单元的分配电压，并且如果比较结果是通过，则调整分配电压直到分配电压高于第二验证电压 同时比较分配电压和第二验证电压。

公开(公告)号：US20170125128A1

公开(公告)日：2017-05-04

申请号：US15207774

申请日：2016-07-12

申请人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

发明人： JI-SANG LEE ,  SANG-SOO PARK ,  DONG-KYO SHIM

IPC分类号： G11C29/56 ,  G11C8/10 ,  G11C7/12 ,  G11C7/14 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C29/1201 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/12 ,  G11C7/14 ,  G11C7/222 ,  G11C8/10 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C27/02 ,  G11C29/42 ,  G11C29/50012 ,  G11C29/52 ,  G11C29/56008 ,  G11C2029/0411 ,  G11C2029/5004 ,  G11C2211/5642

摘要： A nonvolatile memory device with a memory cell array including a plurality of memory cells coupled to first through M-th wordlines and first through N-th bitlines (M>2, N>2), and a page buffer circuit including first through N-th page buffers that are coupled to the first through N-th bitlines, respectively, and generate first through N-th output data, respectively. A K-th page buffer includes first through L-th latches which generate read data by sampling a voltage of a K-th output line, which is discharged through a K-th bitline, at different sampling timings after a read voltage is applied to a P-th wordline (K≦N, L>1, P≦M). The K-th page buffer outputs the first output data if an error in the read data of the first latch is correctable.

公开(公告)号：US08451663B2

公开(公告)日：2013-05-28

申请号：US13053343

申请日：2011-03-22

申请人： Ji-Sang Lee

发明人： Ji-Sang Lee

IPC分类号： G11C11/34 ,  G11C16/34 ,  G11C16/28

CPC分类号： G11C16/04 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3454 ,  G11C2211/5621

摘要： A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括在连接到字线的多个存储器单元中编程目标存储器单元，对所述多个存储器单元执行第一感测操作，并且基于所述目标存储器单元选择性地对所述目标存储器单元执行第二感测操作 这是第一感测操作的结果。

公开(公告)号：US20120137067A1

公开(公告)日：2012-05-31

申请号：US13094192

申请日：2011-04-26

申请人： Ji-Sang Lee ,  Kihwan Choi

发明人： Ji-Sang Lee ,  Kihwan Choi

IPC分类号： G06F12/00 ,  G11C16/26

CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3418

摘要： In one embodiment, the method includes receiving a request to read data stored in a first memory cell associated with a first word line, and performing a first read operation on at least one memory cell associated with a second word line in response to the request. The second word line follows the first word line in a word line programming order, and the first read operation is performed over a first time period. The method further includes performing a second read operation on the first memory cell based on output from the first read operation. The second read operation is performed for a second time period, and the first time period is shorter than the second time period if output from performing the first read operation indicates the first memory cell is not coupled.

摘要翻译： 在一个实施例中，该方法包括接收读取存储在与第一字线相关联的第一存储器单元中的数据的请求，以及响应于该请求对与第二字线相关联的至少一个存储器单元执行第一读取操作。 第二字线在字线编程顺序中跟随第一字线，并且在第一时间段执行第一读取操作。 该方法还包括基于来自第一读取操作的输出对第一存储器单元执行第二读取操作。 如果从执行第一读取操作的输出指示第一存储器单元没有耦合，则第二次读取操作执行第二时间段，并且第一时间段比第二时间段短。