公开(公告)号：US08399364B2

公开(公告)日：2013-03-19

申请号：US13019636

申请日：2011-02-02

Applicant: Kil-chul Kim ,  Jong-cheol Lee ,  Ki-vin Im ,  Jae-hyun Yeo

Inventor： Kil-chul Kim ,  Jong-cheol Lee ,  Ki-vin Im ,  Jae-hyun Yeo

IPC: H01L21/471

CPC classification number: H01L28/40 ,  H01L27/1085 ,  H01L27/11568

Abstract: Methods of manufacturing semiconductor devices including multilayer dielectric layers are disclosed. The methods include forming a multilayer dielectric layer including metal atoms and silicon atoms on a semiconductor substrate. The multilayer dielectric layer includes at least two crystalline metal silicate layers having different silicon concentrations. The multilayer dielectric layer may be used, for example, as a dielectric layer for a capacitor, or as a blocking layer for a nonvolatile memory device.

Abstract translation: 公开了制造包括多层电介质层的半导体器件的方法。 所述方法包括在半导体衬底上形成包括金属原子和硅原子的多层电介质层。 多层介电层包括至少两个具有不同硅浓度的结晶金属硅酸盐层。 多层介电层可以用作电容器的介质层，也可以用作非易失性存储器件的阻挡层。

公开(公告)号：US08343844B2

公开(公告)日：2013-01-01

申请号：US13071927

申请日：2011-03-25

Applicant: Wandon Kim ,  Jong Cheol Lee ,  Jin Yong Kim ,  Beom Seok Kim ,  Yong-Suk Tak ,  Kyuho Cho ,  Ohseong Kwon

Inventor： Wandon Kim ,  Jong Cheol Lee ,  Jin Yong Kim ,  Beom Seok Kim ,  Yong-Suk Tak ,  Kyuho Cho ,  Ohseong Kwon

IPC: H01L21/20

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.

Abstract translation: 制造半导体器件的电容器的方法包括在半导体衬底上形成高k电介质图案，所述高k电介质图案具有包括孔的柱状，在高k的孔中形成下电极 电介质图案，在下电极的上表面上局部形成阻挡绝缘图案，以及形成覆盖高k电介质图案的上电极和阻挡绝缘图案。

公开(公告)号：US08258064B2

公开(公告)日：2012-09-04

申请号：US12909947

申请日：2010-10-22

Applicant: Jong-cheol Lee ,  Ki-yeon Park ,  Se-hoon Oh ,  Youn-soo Kim

Inventor： Jong-cheol Lee ,  Ki-yeon Park ,  Se-hoon Oh ,  Youn-soo Kim

IPC: H01L21/31 ,  H01L21/283

CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531 ,  H01L21/02145 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02208 ,  H01L21/0228 ,  H01L28/40

Abstract: Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Abstract translation: 提供形成金属硅酸盐层的方法和制造包括金属硅酸盐层的半导体器件的方法，形成金属硅酸盐层的方法包括使用多个硅前体形成金属硅酸盐。 硅前体是其中与硅结合的配体具有相同分子结构的均质硅前体。

公开(公告)号：US20110242727A1

公开(公告)日：2011-10-06

申请号：US13076950

申请日：2011-03-31

Applicant: Wan-Don KIM ,  Beom-Seok Kim ,  Jong-Cheol Lee ,  Kyu-Ho Cho ,  Jin-Yong Kim ,  Oh-Seong Kwon ,  Yong-Suk Tak

Inventor： Wan-Don KIM ,  Beom-Seok Kim ,  Jong-Cheol Lee ,  Kyu-Ho Cho ,  Jin-Yong Kim ,  Oh-Seong Kwon ,  Yong-Suk Tak

IPC: H01G4/06

CPC classification number: H01G4/1209 ,  H01G4/002

Abstract: A capacitor may include a lower electrode structure, a dielectric layer and an upper electrode structure. The lower electrode structure may include a first lower pattern, a first deformation-preventing layer pattern and a second lower pattern. The first lower pattern may have a cylindrical shape. The first deformation-preventing layer pattern may be formed on an inner surface of the first lower pattern. The second lower pattern may be formed on the first deformation-preventing layer pattern. The dielectric layer may be formed on the lower electrode structure. The upper electrode structure may be formed on the dielectric layer. Thus, the capacitor may have a high capacitance and improved electrical characteristics.

Abstract translation: 电容器可以包括下电极结构，电介质层和上电极结构。 下部电极结构可以包括第一下部图案，第一防变形图案图案和第二下部图案。 第一下部图案可以具有圆柱形形状。 第一防变形图案图案可以形成在第一下图案的内表面上。 第二下图案可以形成在第一抗变形层图案上。 电介质层可以形成在下电极结构上。 上电极结构可以形成在电介质层上。 因此，电容器可以具有高电容和改善的电特性。

公开(公告)号：US20110237043A1

公开(公告)日：2011-09-29

申请号：US13071927

申请日：2011-03-25

Applicant: Wandon KIM ,  Jong Cheol Lee ,  Jin Yong Kim ,  Beom Seok Kim ,  Yong-Suk Tak ,  Kyuho Cho ,  Ohseong Kwon

Inventor： Wandon KIM ,  Jong Cheol Lee ,  Jin Yong Kim ,  Beom Seok Kim ,  Yong-Suk Tak ,  Kyuho Cho ,  Ohseong Kwon

IPC: H01L21/02

CPC classification number: H01L27/10852 ,  H01L28/91

Abstract: A method of manufacturing a capacitor of a semiconductor device includes forming a high-k dielectric pattern on a semiconductor substrate, the high-k dielectric pattern having a pillar shape including a hole therein, forming a lower electrode in the hole of the high-k dielectric pattern, locally forming a blocking insulating pattern on an upper surface of the lower electrode, and forming an upper electrode covering the high-k dielectric pattern and the blocking insulating pattern.

Abstract translation: 制造半导体器件的电容器的方法包括在半导体衬底上形成高k电介质图案，所述高k电介质图案具有包括孔的柱状，在高k的孔中形成下电极 电介质图案，在下电极的上表面上局部形成阻挡绝缘图案，以及形成覆盖高k电介质图案的上电极和阻挡绝缘图案。

公开(公告)号：US07824501B2

公开(公告)日：2010-11-02

申请号：US11781334

申请日：2007-07-23

Applicant: Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

Inventor： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

IPC: B08B9/08 ,  B08B3/08 ,  B08B3/10 ,  B08B5/00

CPC classification number: C23C16/45525 ,  C23C16/4401 ,  C23C16/45544

Abstract: Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.

Abstract translation: 提供了一种在电介质层沉积工艺期间清洁原子层沉积设备的蒸发器的原位方法，以防止蒸发器和原子层沉积设备中的喷嘴堵塞。 在电介质层沉积过程中，重复以下步骤：将用于电介质层沉积的第一源气体供应到原子层沉积设备的腔室中; 净化第一源气; 将第二源气体供应到原子层沉积设备的腔室中; 吹扫第二源气体时，在供给用于电介质层沉积的第一源气体并再次供应第一源气体之前执行清洗蒸发器的原位方法。

公开(公告)号：US07791125B2

公开(公告)日：2010-09-07

申请号：US11881562

申请日：2007-07-27

Applicant: Hoon-Sang Choi ,  Jong-Cheol Lee ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Sang-Yeol Kang

Inventor： Hoon-Sang Choi ,  Jong-Cheol Lee ,  Ki-Vin Im ,  Jae-Hyun Yeo ,  Eun-Ae Chung ,  Sang-Yeol Kang

IPC: H01L27/108

CPC classification number: H01L21/02194 ,  H01L21/0228 ,  H01L21/02318 ,  H01L21/31604 ,  H01L21/31641 ,  H01L21/31645 ,  H01L28/91

Abstract: A method of forming a semiconductor device includes loading a semiconductor substrate into a reaction chamber, and providing metal organic precursors including hafnium and zirconium into the reaction chamber to form hafnium-zirconium oxide (HfxZr1-xO; 0

Abstract translation: 一种形成半导体器件的方法包括将半导体衬底加载到反应室中，并向反应室中提供包括铪和锆的金属有机前体以形成铪锆氧化物（Hf x Zr 1-x O; 0

公开(公告)号：US20100167554A1

公开(公告)日：2010-07-01

申请号：US12648377

申请日：2009-12-29

Applicant: Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

Inventor： Jong-Cheol LEE ,  Ki-Yeon PARK ,  Jun-Noh LEE

IPC: H01L21/469

CPC classification number: C23C16/4554 ,  C23C16/45531 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3141 ,  H01L28/60 ,  H01L29/66575 ,  H01L29/78

Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.

Abstract translation: 在形成具有均匀构成材料组成的目标层的方法中，包括第一中心原子和配体的第一前体在物体的第一反应位置被化学吸附。 然后除去配体或第一中心原子以形成第二反应位点。 包括第二中心原子的第二前体然后在第二反应位点被化学吸附。

公开(公告)号：US07656723B2

公开(公告)日：2010-02-02

申请号：US12347239

申请日：2008-12-31

Applicant: Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

Inventor： Nam-Seog Kim ,  Jong-Cheol Lee ,  Hak-Soo Yu ,  Uk-Rae Cho

IPC: G11C7/22

CPC classification number: G11C11/417 ,  G11C7/18 ,  G11C8/12

Abstract: A semiconductor memory device has a hierarchical bit line structure. The semiconductor memory device may include first and second memory cell clusters, which share the same bit line pair and are divided operationally; third and fourth memory cell clusters, which are connected respectively corresponding to word lines coupled with the first and second memory cell clusters, and which share a bit line pair different from the bit line pair and are divided operationally; and a column pass gate for switching one of bit line pairs connected with the first to fourth memory cell clusters, to a common sense amplifier, in response to a column selection signal. Whereby an operating speed decrease caused by load of peripheral circuits connected to the bit line is improved, and the number of column pass gates is reduced substantially with a reduction of chip size.

Abstract translation: 半导体存储器件具有分层位线结构。 半导体存储器件可以包括第一和第二存储器单元簇，其共享相同的位线对并且在操作上被分割; 第三和第四存储单元簇，其分别对应于与第一和第二存储器单元簇耦合的字线，并且共享与位线对不同的位线对，并在操作上分割; 以及用于响应于列选择信号将与第一至第四存储器单元簇连接的位线对之一切换到公共读出放大器的列通路。 由此，连接到位线的外围电路的负载导致的工作速度降低得到改善，并且随着芯片尺寸的减小，列通孔的数量基本上减小。

公开(公告)号：US07570529B2

公开(公告)日：2009-08-04

申请号：US11830142

申请日：2007-07-30

Applicant: Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

Inventor： Myeong-O Kim ,  Soo-Hwan Kim ,  Jong-Cheol Lee

IPC: G11C7/00

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C2207/005

Abstract: A sense amplifier circuit of a semiconductor memory device and a method of operating the same, in which the sense amplifier circuit includes a bit line sense amplifier connected with a bit line to sense and amplify a signal of the bit line, and a calibration circuit calibrating a voltage level of the bit line based on a logic threshold value of the bit line sense amplifier. The bit line sense amplifier senses and amplifies the signal of the bit line after the voltage level of the bit line is calibrated. The bit line sense amplifier may include a 2-stage cascade latch, which includes a first inverter having an input terminal connected with the bit line; and a second inverter which has an input terminal connected with an output terminal of the first inverter and an output terminal connected with the bit line and is enabled/disabled in response to a sensing control signal. The calibration circuit includes a switch element that is connected between the output terminal of the first inverter and the bit line and is turned on or off in response to a calibration control signal.

Abstract translation: 半导体存储器件的读出放大器电路及其操作方法，其中读出放大器电路包括与位线连接的位线读出放大器，以检测和放大位线的信号，校准电路校准 基于位线读出放大器的逻辑阈值的位线的电压电平。 位线检测放大器在校准位线的电压电平后，感测并放大位线的信号。 位线读出放大器可以包括2级级联锁存器，其包括具有与位线连接的输入端的第一反相器; 以及第二反相器，其具有与第一反相器的输出端子连接的输入端子和与位线连接的输出端子，并且响应于感测控制信号而被允许/禁止。 校准电路包括开关元件，其连接在第一反相器的输出端和位线之间，并响应于校准控制信号而导通或截止。