公开(公告)号：US20060073670A1

公开(公告)日：2006-04-06

申请号：US11243397

申请日：2005-10-03

Applicant: Yong-Kug Bae ,  Kwang-Sub Yoon ,  Young-Wook Park ,  Jung-Hyeon Lee

Inventor： Yong-Kug Bae ,  Kwang-Sub Yoon ,  Young-Wook Park ,  Jung-Hyeon Lee

IPC: H01L21/20 ,  H01L21/4763 ,  H01L21/8242

CPC classification number: H01L28/91 ,  H01L21/7682 ,  H01L27/10852 ,  H01L27/10894

Abstract: In one embodiment, first and second multi-layer pattern structures are formed over first and second regions of a substrate, respectively. The first and second multi-layer pattern structures include first and second support layer patterns, respectively. The first and second multi-layer pattern structures define first and second openings, respectively. The first and second openings partially expose a portion of the first region and a portion of the second region, respectively. First and second liner patterns are formed on an inner face of the first opening and an inner face of the second opening, respectively. A first etching process is performed on the first multi-layer pattern structure until the first support layer pattern is removed. A second etching process is performed to remove the second multi-layer pattern structure except for the second support layer pattern.

Abstract translation: 在一个实施例中，分别在衬底的第一和第二区域上形成第一和第二多层图案结构。 第一和第二多层图案结构分别包括第一和第二支撑层图案。 第一和第二多层图案结构分别限定第一和第二开口。 第一和第二开口分别部分地暴露第一区域的一部分和第二区域的一部分。 第一和第二衬里图案分别形成在第一开口的内表面和第二开口的内表面上。 对第一多层图案结构进行第一蚀刻处理，直到第一支撑层图案被去除。 执行第二蚀刻处理以除去除了第二支撑层图案之外的第二多层图案结构。

公开(公告)号：US06885052B2

公开(公告)日：2005-04-26

申请号：US09790240

申请日：2001-02-21

Applicant: Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

Inventor： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC: H01L27/10 ,  H01L21/60 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

Abstract translation: 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US06218204B1

公开(公告)日：2001-04-17

申请号：US09326557

申请日：1999-06-07

Applicant: Jin-Seog Hong ,  Jung-Hyeon Lee ,  Ho-Young Kang

Inventor： Jin-Seog Hong ,  Jung-Hyeon Lee ,  Ho-Young Kang

IPC: H01L2100

CPC classification number: H01L22/12 ,  H01L27/10852

Abstract: Reduction in focusing error of an exposure process includes forming a conductive layer over a wafer whose topology is to be measured by a capacitance gauge. The conductive layer is thick enough such that differences in capacitance measured by the capacitance gauge tracking apparatus are not due to differences in underlying material and structure on the wafer. Thus, accurate measurement of the real topology of wafer by capacitance gauge tracking apparatus may be realized. As a result, the subsequent exposure processing is reliable.

Abstract translation: 降低曝光处理的聚焦误差包括在通过电容量规测量其拓扑结构的晶片上形成导电层。 导电层足够厚，使得由电容量规跟踪装置测量的电容差异不是由于晶片上的下面的材料和结构的差异引起的。 因此，可以实现电容计跟踪装置对晶片的真实拓扑的精确测量。 结果，随后的曝光处理是可靠的。

公开(公告)号：US20060291077A1

公开(公告)日：2006-12-28

申请号：US11451580

申请日：2006-06-13

Applicant: Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

Inventor： Woo-Seok Shim ,  Jung-Hyeon Lee ,  Young-Koog Han ,  Kwang-Sub Yoon ,  Si-Hyeung Lee

IPC: G02B7/02

CPC classification number: G02B7/00 ,  G03F7/701 ,  G03F7/70825

Abstract: In an optical member holder and a projection exposure apparatus having the same, a light beam radiated from a light source may be formed into light having a desired shape by selecting one of a plurality of optical elements. An optical element holder may include a support member to support the plurality of optical elements, a first driving section to move or rotate the support member to select one of the optical elements, and a second driving section to rotate the selected optical element to adjust an arrangement direction thereof. The light formed by the selected optical element may be directed through a reticle.

Abstract translation: 在具有该光学构件保持器和投影曝光设备的光学构件保持器和投影曝光设备中，从光源辐射的光束可以通过选择多个光学元件之一形成具有所需形状的光。 光学元件保持器可以包括用于支撑多个光学元件的支撑构件，用于移动或旋转支撑构件以选择一个光学元件的第一驱动部分和第二驱动部分，以旋转所选择的光学元件以调整 排列方向。 由所选择的光学元件形成的光可以被引导通过掩模版。

公开(公告)号：US07132708B2

公开(公告)日：2006-11-07

申请号：US11054593

申请日：2005-02-09

Applicant: Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

Inventor： Tae-hyuk Ahn ,  Myeong-cheol Kim ,  Jung-hyeon Lee ,  Byeong-yun Nam ,  Gyung-jin Min

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided. The semiconductor memory device having self-aligned contacts includes a plurality of gate electrode patterns arranged in parallel on a semiconductor substrate, in which a plurality of first spacers are formed along the sidewalls of the gate electrode patterns, a first interdielectric layer formed on the entire surface of a resultant in which the first spacers are formed, a plurality of bit line patterns arranged in parallel on the first interdielectric layer to be perpendicular to the gate electrode patterns, in which a plurality of second spacers are formed along the sidewalls of the bit line patterns, a plurality of contacts for bit lines self-aligned with the first spacers, a second interdielectric layer formed on the entire surface of a resultant in which the second spacers are formed, and a plurality of contacts for storage electrodes simultaneously self-aligned with the second and first spacers.

Abstract translation: 一种具有自对准触点的半导体存储器件及其制造方法，其特征在于能够防止位线触点和存储电极触点之间的短路，并提高加工余量。 具有自对准触点的半导体存储器件包括平行布置在半导体衬底上的多个栅电极图案，其中多个第一间隔物沿着栅电极图案的侧壁形成，第一绝缘层整体形成 其中形成有第一间隔物的结果的表面，在第一电介质层上平行布置成垂直于栅极电极图案的多个位线图案，其中沿着该位的侧壁形成多个第二间隔物 线图案，用于与第一间隔物自对准的位线的多个触点，形成在其中形成有第二间隔物的结果的整个表面上的第二电介质层和用于存储电极的多个触点同时自对准 与第二和第一间隔物。

公开(公告)号：US20050089776A1

公开(公告)日：2005-04-28

申请号：US10937398

申请日：2004-09-10

Applicant: Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

Inventor： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC: G03C5/00 ,  G03F7/40 ,  H01L21/027 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/544

CPC classification number: H01L22/34 ,  G03F7/40 ,  H01L21/0273

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract translation: 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙

公开(公告)号：US06492701B1

公开(公告)日：2002-12-10

申请号：US09324072

申请日：1999-06-01

Applicant: In-sung Kim ,  Jung-hyeon Lee ,  Han-ku Cho

Inventor： In-sung Kim ,  Jung-hyeon Lee ,  Han-ku Cho

IPC: H01L310232

CPC classification number: H01L21/0276 ,  H01L21/28044 ,  H01L21/28061 ,  H01L21/76802

Abstract: A semiconductor device including an anti-reflective cap and spacer, a method of manufacturing the same, and a method of forming a photoresist pattern using the same are provided. The semiconductor device according to the present invention includes an anti-reflective cap and an anti-reflective spacer on an upper surface and side walls of a reflective pattern formed on the semiconductor substrate. Therefore, the deformation of the photoresist pattern by the light reflected from the reflective pattern is minimized during a photolithography process.

Abstract translation: 提供了包括抗反射盖和间隔物的半导体器件，其制造方法和使用其形成光致抗蚀剂图案的方法。 根据本发明的半导体器件包括在半导体衬底上形成的反射图案的上表面上的抗反射盖和抗反射隔板。 因此，在光刻工艺中，由反射图案反射的光使光刻胶图案的变形最小化。

公开(公告)号：US08431331B2

公开(公告)日：2013-04-30

申请号：US12267687

申请日：2008-11-10

Applicant: Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

Inventor： Yool Kang ,  Suk-joo Lee ,  Jung-hyeon Lee ,  Shi-yong Yi

IPC: G03F7/40

CPC classification number: H01L21/027 ,  G03F7/0035 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/0338 ,  H01L21/32139

Abstract: A method of forming fine patterns of a semiconductor device according to a double patterning process that uses acid diffusion is provided. In this method, a plurality of first mask patterns are formed on a substrate so as to be separated from one another. A capping film including an acid source is formed on sidewalls and an upper surface of each of the plurality of first mask patterns. A second mask layer is formed on the capping films. A plurality of acid diffused regions are formed within the second mask layer by diffusing acid obtained from the acid source from the capping films into the second mask layer. A plurality of second mask patterns are formed of residual parts of the second mask layer which remain in the first spaces after removing the acid diffused regions of the second mask layer.

Abstract translation: 提供了根据使用酸扩散的双重图案化工艺形成半导体器件的精细图案的方法。 在该方法中，在基板上形成多个第一掩模图案以彼此分离。 在多个第一掩模图案的每一个的侧壁和上表面上形成包括酸源的封盖膜。 在封盖膜上形成第二掩模层。 通过将从酸源获得的酸从封盖膜扩散到第二掩模层中，在第二掩模层内形成多个酸扩散区。 多个第二掩模图案由除去第二掩模层的酸扩散区域之后残留在第一间隙中的第二掩模层的残留部分形成。

公开(公告)号：US07892982B2

公开(公告)日：2011-02-22

申请号：US11978718

申请日：2007-10-30

Applicant: Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

Inventor： Doo-youl Lee ,  Pan-suk Kwak ,  Sung-gon Jung ,  Jung-hyeon Lee ,  Suk-joo Lee ,  Cha-won Koh ,  Ji-young Lee

IPC: H01L21/302

CPC classification number: H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L21/76838

Abstract: A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.

Abstract translation: 用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度 在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案， 在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为 蚀刻掩模以形成蚀刻膜图案。

公开(公告)号：US07670761B2

公开(公告)日：2010-03-02

申请号：US12219214

申请日：2008-07-17

Applicant: Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

Inventor： Doo-youl Lee ,  Gi-sung Yeo ,  Han-ku Cho ,  Jung-hyeon Lee

IPC: G03F1/00

CPC classification number: H01L22/34 ,  G03F7/40 ,  H01L21/0273

Abstract: In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.

Abstract translation: 在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径 位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案， 位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上 首先回流钥匙