公开(公告)号：US20080242035A1

公开(公告)日：2008-10-02

申请号：US12014136

申请日：2008-01-15

申请人： Takuya FUTASE ,  Keiichiro Kashihara ,  Shigenari Okada

发明人： Takuya FUTASE ,  Keiichiro Kashihara ,  Shigenari Okada

IPC分类号： H01L21/336

CPC分类号： H01L29/7846 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/7843

摘要： The performance of the semiconductor device which formed the metal silicide layer in the salicide process is improved. An element isolation region is formed in a semiconductor substrate by the STI method, a gate insulating film is formed, a gate electrode is formed, n+ type semiconductor region and p+ type semiconductor region for source/drains are formed, a metallic film is formed on a semiconductor substrate, and a barrier film is formed on a metallic film. And after forming the metal silicide layer to which a metallic film, and a gate electrode, n+ type semiconductor region and p+ type semiconductor region are made to react by performing first heat treatment, a barrier film, and an unreacted metallic film are removed, and the metal silicide layer is left. An element isolation region makes compressive stress act on a semiconductor substrate. A barrier film is a film which makes a semiconductor substrate generate tensile stress, and the metal silicide layer which consists of mono-silicide MSi of metallic element M which forms a metallic film is formed in the first heat treatment.

摘要翻译： 提高了在自对准硅化物工艺中形成金属硅化物层的半导体器件的性能。 通过STI法在半导体衬底中形成元件隔离区域，形成栅极绝缘膜，形成栅电极，n + +型半导体区域和p + 形成用于源极/漏极的半导体区域，在半导体衬底上形成金属膜，并且在金属膜上形成阻挡膜。 并且在形成金属硅化物层之后，通过执行第一次金属硅化物层使金属膜和栅极，n + +型半导体区域和p + +型半导体区域反应 除去热处理，阻挡膜和未反应的金属膜，留下金属硅化物层。 元件隔离区使压缩应力作用在半导体衬底上。 阻挡膜是使半导体基板产生拉伸应力的膜，在第一热处理中形成由形成金属膜的金属元素M的单硅化物MSi构成的金属硅化物层。

公开(公告)号：US20070077736A1

公开(公告)日：2007-04-05

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/04

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06078072A

公开(公告)日：2000-06-20

申请号：US73834

申请日：1998-05-06

申请人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

发明人： Tomonori Okudaira ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L29/76 ,  H01L27/108 ,  H01L29/94 ,  H01L31/113

CPC分类号： H01L27/10852 ,  H01L28/60 ,  H01L28/55

摘要： A lower electrode layer 1 of a capacitor 10 is formed by sputtering performed at a temperature lower than 450.degree. C. in an atmosphere containing oxygen, and thereby the lower electrode layer 1 thus formed contains oxygen. Thereby, a method of manufacturing a semiconductor device having the capacitor can suppress current leak, and can prevent peeling of an electrode.

摘要翻译： 电容器10的下电极层1通过在低于450℃的温度下在含氧气氛中进行溅射而形成，由此形成的下电极层1含有氧。 因此，制造具有电容器的半导体器件的方法可以抑制电流泄漏，并且可以防止电极的剥离。

公开(公告)号：US5567964A

公开(公告)日：1996-10-22

申请号：US526392

申请日：1995-09-11

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/088 ,  H01L29/76

CPC分类号： H01L27/10852 ,  H01L27/11502 ,  Y10S257/90

摘要： An object of the invention is to provide a capacitor having good anti-leak characteristics and good breakdown voltage characteristics. A transfer gate transistor having source/drain regions is formed on a surface of a silicon substrate. There is provided a lower electrode layer connected to the source/drain region through a plug layer which fills a contact hole formed at an interlayer insulating film. On the lower electrode layer, there is formed a capacitor insulating layer which includes a ferroelectric layer and exposes at least a sidewall surface of the lower electrode layer. The exposed sidewall surface of the lower electrode layer is covered with a sidewall insulating layer which is formed on a top surface of the interlayer insulating film and has a sidewall spacer configuration. The lower electrode layer is covered with an upper electrode layer with the sidewall insulating layer and capacitor insulating layer therebetween.

摘要翻译： 本发明的目的是提供具有良好的防漏电特性和良好的击穿电压特性的电容器。 具有源极/漏极区域的传输栅极晶体管形成在硅衬底的表面上。 提供了一个下电极层，该下电极层通过填充形成在层间绝缘膜上的接触孔的插塞层连接到源/漏区。 在下电极层上形成电容绝缘层，该电容器绝缘层包括铁电体层，并暴露至少下电极层的侧壁表面。 下电极层的露出的侧壁表面被形成在层间绝缘膜的顶表面上并具有侧壁间隔物构造的侧壁绝缘层覆盖。 下电极层覆盖有上电极层，其间具有侧壁绝缘层和电容器绝缘层。

公开(公告)号：US5382817A

公开(公告)日：1995-01-17

申请号：US20082

申请日：1993-02-19

申请人： Keiichiro Kashihara ,  Hiromi Itoh

发明人： Keiichiro Kashihara ,  Hiromi Itoh

IPC分类号： H01L21/02 ,  H01L27/115 ,  H01L29/92

CPC分类号： H01L27/11502 ,  H01L28/55 ,  H01L28/75 ,  Y10S257/915

摘要： A semiconductor device capable of improving pressure-resistant and leakage-resistant characteristics of a stacked type capacitor formed on a planarized insulating layer. The semiconductor device includes a plug electrode layer 313 of at least one material selected from the group consisting of TiN, Ti, W, and WN, buried in a contact hole 311a of an interlayer insulating films 311 and extending on and along the upper surface of interlayer insulating film 311. As a result, creation of a stepped portion on platinum layer 314 constituting a capacitor lower electrode to be formed on the plug electrode 313 is prevented, and the thickness of a PZT film 315 to be formed on platinum layer 314 is not disadvantageously made thin at the stepped portion. Therefore, the space between a capacitor upper electrode 316 and platinum layer 314 constituting the capacitor lower electrode can not be made narrow, and an electric field between platinum layer 314 and capacitor upper electrode 316 is made uniform, enhancing pressure-resistant and leakage-resistant characteristics. Also, a silicification reaction of platinum layer 314 is prevented due to plug electrode layer 313. In addition, when plug electrode layer 313 is formed of Ti or TiN, adhesion of plug electrode layer 313 and interlayer insulating film 311 is improved, and thus separation of platinum layer 314 is prevented.

摘要翻译： 一种能够提高形成在平坦化绝缘层上的叠层型电容器的耐压和耐漏电特性的半导体器件。 半导体器件包括从由TiN，Ti，W和WN组成的组中选择的至少一种材料的插塞电极层313，该TiN，Ti，W和WN埋在层间绝缘膜311的接触孔311a中并在其上表面上延伸 结果，防止了在形成在插头电极313上的构成电容器下电极的铂层314上形成台阶部分，并且形成在铂层314上的PZT膜315的厚度为 不利于在阶梯部分变薄。 因此，构成电容器下电极的电容器上电极316和铂层314之间的空间不能变窄，铂层314和电容器上电极316之间的电场均匀，增强耐压和耐漏电 特点 此外，由于塞电极层313，可防止铂层314的硅化反应。此外，当塞电极层313由Ti或TiN形成时，插塞电极层313和层间绝缘膜311的粘附性提高，因此分离 的铂层314。

公开(公告)号：US20110207317A1

公开(公告)日：2011-08-25

申请号：US13053733

申请日：2011-03-22

申请人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

发明人： Toshiaki Tsutsumi ,  Tomonori Okudaira ,  Keiichiro Kashihara ,  Tadashi Yamaguchi

IPC分类号： H01L21/768

CPC分类号： H01L23/485 ,  H01L21/28518 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having a metal silicide layer which can suppress the malfunction and the increase in power consumption of the device. The semiconductor device has a semiconductor substrate containing silicon and having a main surface, first and second impurity diffusion layers formed in the main surface of the semiconductor substrate, a metal silicide formed over the second impurity diffusion layer, and a silicon nitride film and a first interlayer insulation film sequentially stacked over the metal silicide. In the semiconductor device, a contact hole penetrating through the silicon nitride film and the first interlayer insulation film, and reaching the surface of the metal silicide is formed. The thickness of a portion of the metal silicide situated immediately under the contact hole is smaller than the thickness of a portion of the metal silicide situated around the contact hole.

摘要翻译： 提供了具有金属硅化物层的半导体器件，其可以抑制器件的故障和功率消耗的增加。 半导体器件具有包含硅并具有主表面的半导体衬底，形成在半导体衬底的主表面中的第一和第二杂质扩散层，形成在第二杂质扩散层上的金属硅化物，以及氮化硅膜和第一 层间绝缘膜依次层叠在金属硅化物上。 在半导体器件中，形成穿过氮化硅膜和第一层间绝缘膜并到达金属硅化物表面的接触孔。 位于接触孔正下方的金属硅化物的一部分的厚度小于位于接触孔周围的金属硅化物的一部分的厚度。

公开(公告)号：US20110037103A1

公开(公告)日：2011-02-17

申请号：US12852259

申请日：2010-08-06

申请人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

发明人： Tadashi YAMAGUCHI ,  Keiichiro KASHIHARA ,  Toshiaki TSUTSUMI ,  Tomonori OKUDAIRA ,  Kotaro KIHARA

IPC分类号： H01L27/105 ,  H01L21/8239 ,  H01L29/04

CPC分类号： H01L27/105 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

摘要： To improve performance of a semiconductor device. Over a semiconductor substrate, a plurality of p-channel type MISFETs for logic, a plurality of n-channel type MISFETs for logic, a plurality of p-channel type MISFETs for memory, and a plurality of n-channel type MISFETs for memory are mixedly mounted. At least a part of the p-channel type MISFETs for logic have each a source/drain region constituted by silicon-germanium, and all the n-channel type MISFETs for logic have each a source/drain region constituted by silicon. All the p-channel type MISFETs for memory have each a source/drain region constituted by silicon, and all the n-channel type MISFETs for memory have each a source/drain region constituted by silicon.

摘要翻译： 提高半导体器件的性能。 在半导体衬底上，用于逻辑的多个p沟道型MISFET，用于逻辑的多个n沟道型MISFET，用于存储器的多个p沟道型MISFET和用于存储器的多个n沟道型MISFET， 混合安装。 用于逻辑的p沟道型MISFET的至少一部分具有由硅 - 锗构成的源极/漏极区域，并且用于逻辑的所有n沟道型MISFET具有由硅构成的源极/漏极区域。 用于存储器的所有p沟道型MISFET具有由硅构成的源极/漏极区域，并且用于存储器的所有n沟道型MISFET具有由硅构成的源极/漏极区域。

公开(公告)号：US07872314B2

公开(公告)日：2011-01-18

申请号：US12727334

申请日：2010-03-19

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US07696050B2

公开(公告)日：2010-04-13

申请号：US11537208

申请日：2006-09-29

申请人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

发明人： Tadashi Yamaguchi ,  Keiichiro Kashihara ,  Tomonori Okudaira ,  Toshiaki Tsutsumi

IPC分类号： H01L21/336

CPC分类号： H01L21/823814 ,  H01L21/26506 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： An N-type source region and an N-type drain region of N-channel type MISFETs are implanted with ions (containing at least one of F, Si, C, Ge, Ne, Ar and Kr) with P-channel type MISFETs being covered by a mask layer. Then, each gate electrode, source region and drain region of the N- and P-channel type MISFETs are subjected to silicidation (containing at least one of Ni, Ti, Co, Pd, Pt and Er). This can suppress a drain-to-body off-leakage current (substrate leakage current) in the N-channel type MISFETs without degrading the drain-to-body off-leakage current in the P-channel type MISFETs.

摘要翻译： 离子（含有F，Si，C，Ge，Ne，Ar和Kr中的至少一个）注入N沟道型MISFET的N型源极区域和N型漏极区域，P沟道型MISFET为 被掩模层覆盖。 然后，对N沟道型MISFET和P沟道型MISFET的各栅电极，源极区和漏极区进行硅化（含有Ni，Ti，Co，Pd，Pt和Er中的至少一种）。 这可以抑制N沟道型MISFET中的漏 - 漏泄漏电流（衬底泄漏电流），而不会降低P沟道型MISFET中的漏 - 漏泄漏电流。

公开(公告)号：US06746876B2

公开(公告)日：2004-06-08

申请号：US10310765

申请日：2002-12-06

申请人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

发明人： Hiromi Itoh ,  Yoshikazu Tsunemine ,  Keiichiro Kashihara ,  Akie Yutani ,  Tomonori Okudaira

IPC分类号： H01L218242

CPC分类号： H01L28/55 ,  H01L28/91

摘要： A method for manufacturing a capacitor is provided which can form a lower electrode having a high aspect ratio without suffering deterioration of the capacitor electric characteristics even when a platinum-group metal is adopted as the material of the lower electrode and a metal oxide having a high dielectric constant is adopted as the material of the dielectric film. Holes (8) that reach contact plugs (2) are formed in an insulating film (7). Then a dielectric film (9) is formed on the surfaces of the holes (8). Next the dielectric film (9) on the bottoms of the holes (8) are etched away to form holes (18) reaching the contact plugs (2). Lower electrodes (11) are then formed to fill the holes (8) and (18).

摘要翻译： 提供了一种用于制造电容器的方法，即使当采用铂族金属作为下电极的材料时，也可形成具有高纵横比的下电极，而不会降低电容器的电特性，并且具有高的金属氧化物 采用介电常数作为电介质膜的材料。 到达接触塞（2）的孔（8）形成在绝缘膜（7）中。 然后在孔（8）的表面上形成介电膜（9）。 接下来，蚀刻掉孔（8）的底部上的电介质膜（9），以形成到达接触塞（2）的孔（18）。 然后形成下电极（11）以填充孔（8）和（18）。