公开(公告)号：US20150170317A1

公开(公告)日：2015-06-18

申请号：US14132028

申请日：2013-12-18

申请人： Eric C. Samson ,  Murali Ramadoss

发明人： Eric C. Samson ,  Murali Ramadoss

IPC分类号： G06T1/20

CPC分类号： G06T1/20 ,  G06F9/5083 ,  G06F9/5094 ,  Y02D10/22

摘要： In accordance with some embodiments, a system may detect whether or not a workload currently being worked on by two processors is serialized or concurrent. A workload is serialized or a producer consumer workload when the workload is such that one processor must receive the output from the other processor before it can begin. A workload is concurrent if both processors can work on the workload at the same time. In one embodiment, the nature of memory accesses can be used to determine the workload type. For example, when both processors use a shared virtual memory, the memory accesses can be tracked to detect whether serialized or concurrent workloads are involved.

摘要翻译： 根据一些实施例，系统可以检测两个处理器当前正在工作的工作负载是否被序列化或并发。 当工作负载使得一个处理器必须在其开始之前从另一个处理器接收输出时，工作负载被序列化或生产者消费者工作负载。 如果两个处理器可以同时处理工作负载，则工作负载是并发的。 在一个实施例中，存储器访问的性质可以用于确定工作负载类型。 例如，当两个处理器使用共享虚拟内存时，可以跟踪内存访问以检测是否涉及序列化或并发工作负载。

公开(公告)号：US20140198116A1

公开(公告)日：2014-07-17

申请号：US13977261

申请日：2011-12-28

申请人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

发明人： Bryan E. Veal ,  Travis T. Schluessler ,  Murali Ramadoss ,  Balaji Vembu

IPC分类号： G06T1/60

CPC分类号： G06T1/60 ,  G11C16/349

摘要： Methods and devices to augment volatile memory in a graphics subsystem with certain types of non-volatile memory are described. In one embodiment, includes storing one or more static or near-static graphics resources in a non-volatile random access memory (NVRAM). The NVRAM is directly accessible by a graphics processor using at least memory store and load commands. The method also includes a graphics processor executing a graphics application. The graphics processor sends a request using a memory load command for an address corresponding to at least one static or near-static graphics resources stored in the NVRAM. The method also includes directly loading the requested graphics resource from the NVRAM into a cache for the graphics processor in response to the memory load command.

摘要翻译： 描述了在具有某些类型的非易失性存储器的图形子系统中增加易失性存储器的方法和装置。 在一个实施例中，包括将一个或多个静态或近静态图形资源存储在非易失性随机存取存储器（NVRAM）中。 NVRAM可直接由图形处理器使用，至少使用内存存储和加载命令。 该方法还包括执行图形应用的图形处理器。 图形处理器使用存储器加载命令来发送对应于存储在NVRAM中的至少一个静态或近静态图形资源的地址的请求。 该方法还包括响应于存储器加载命令将所请求的图形资源从NVRAM直接加载到图形处理器的高速缓存中。

公开(公告)号：US20130159820A1

公开(公告)日：2013-06-20

申请号：US13327845

申请日：2011-12-16

申请人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

发明人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

IPC分类号： H03M13/09 ,  G06F11/10

CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057

摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

摘要翻译： 公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。 在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。 存储结构是存储多个数据值。 奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。 错误存储空间是存储奇偶校验错误检测的指示。 错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

公开(公告)号：US08411095B2

公开(公告)日：2013-04-02

申请号：US13469395

申请日：2012-05-11

申请人： Eric Samson ,  Murali Ramadoss

发明人： Eric Samson ,  Murali Ramadoss

IPC分类号： G06F13/14 ,  G06F15/00 ,  G06T1/00

CPC分类号： G06T1/00 ,  G06F1/3203 ,  G06F1/324 ,  G06F9/50 ,  G06F11/3409 ,  G06F11/348 ,  G06T1/20 ,  G09G5/001 ,  G09G5/363 ,  G09G2330/021 ,  Y02D10/126 ,  Y02D10/22 ,  Y02D10/34

摘要： In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

公开(公告)号：US20200074713A1

公开(公告)日：2020-03-05

申请号：US16116158

申请日：2018-08-29

申请人： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

发明人： TRAVIS SCHLUESSLER ,  ZACK WATERS ,  MICHAEL APODACA ,  DANIEL JOHNSTON ,  JASON SURPRISE ,  PRASOONKUMAR SURTI ,  SUBRAMANIAM MAIYURAN ,  PETER DOYLE ,  SAURABH SHARMA ,  ANKUR SHAH ,  MURALI RAMADOSS

IPC分类号： G06T15/00 ,  G06T15/80 ,  G06T15/40

摘要： Position-based rendering apparatus and method for multi-die/GPU graphics processing. For example, one embodiment of a method comprises: distributing a plurality of graphics draws to a plurality of graphics processors; performing position-only shading using vertex data associated with tiles of a first draw on a first graphics processor, the first graphics processor responsively generating visibility data for each of the tiles; distributing subsets of the visibility data associated with different subsets of the tiles to different graphics processors; limiting geometry work to be performed on each tile by each graphics processor using the visibility data, each graphics processor to responsively generate rendered tiles; and wherein the rendered tiles are combined to generate a complete image frame.

公开(公告)号：US20190324919A1

公开(公告)日：2019-10-24

申请号：US16457019

申请日：2019-06-28

申请人： Altug Koker ,  Ankur Shah ,  Murali Ramadoss ,  Niranjan Cooray

发明人： Altug Koker ,  Ankur Shah ,  Murali Ramadoss ,  Niranjan Cooray

IPC分类号： G06F12/1009 ,  G06F12/1027

摘要： Systems and methods related to memory paging and memory translation are disclosed. The systems may allow allocation of memory pages with increased diversity in the memory page sizes using page tables dimensioned in a manner that optimizes memory usage by the data structures of the page system.

公开(公告)号：US20190244418A1

公开(公告)日：2019-08-08

申请号：US16269270

申请日：2019-02-06

申请人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

发明人： Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh ,  Devan Burke ,  Philip R. Laws ,  Subramaniam Maiyuran ,  Abhishek R. Appu ,  ElMoustapha Ould-Ahmed-Vall ,  Peter L. Doyle

IPC分类号： G06T15/80 ,  G06F9/50 ,  G06T1/20 ,  G06T5/20

CPC分类号： G06T15/80 ,  G06F9/50 ,  G06F9/5011 ,  G06T1/20 ,  G06T5/20

摘要： An embodiment of a conditional shader apparatus may include a conditional pixel shader to determine if one or more pixels meet a shader condition, and a pixel regrouper communicatively coupled to the conditional pixel shader to regroup pixels based on whether the one or more pixels are determined to meet the shader condition. Another embodiment of a conditional shader apparatus may include a thread analyzer to determine if a set of threads meet a thread condition, and a conditional kernel loader communicatively coupled to the thread analyzer to load an appropriate kernel from a set of two or more kernels based on whether the set of threads are determined to meet the thread condition. Other embodiments are disclosed and claimed.

公开(公告)号：US09678795B2

公开(公告)日：2017-06-13

申请号：US13993089

申请日：2011-12-30

申请人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

发明人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F9/46 ,  G06F9/50 ,  G06F9/48 ,  G06F15/167 ,  G06F9/54 ,  G06F12/14

CPC分类号： G06F9/50 ,  G06F9/4812 ,  G06F9/545 ,  G06F12/1491 ,  G06F15/167

摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

公开(公告)号：US20170091989A1

公开(公告)日：2017-03-30

申请号：US14865933

申请日：2015-09-25

申请人： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

发明人： Murali Ramadoss ,  Balaji Vembu ,  Hema C. Nalluri ,  Michael Apodaca ,  Jeffery S. Boles

IPC分类号： G06T15/80 ,  G06T1/20

CPC分类号： G06T15/80 ,  G06F9/48 ,  G06F9/4881 ,  G06T1/20

摘要： By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments.

公开(公告)号：US09582216B2

公开(公告)日：2017-02-28

申请号：US13977295

申请日：2011-12-28

申请人： Balaji Vembu ,  Murali Ramadoss

发明人： Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F3/06 ,  G06F12/02 ,  G06T1/60 ,  G11C14/00

CPC分类号： G06F3/0638 ,  G06F3/0604 ,  G06F3/0683 ,  G06F12/0292 ,  G06F2212/205 ,  G06T1/60 ,  G11C14/0045 ,  Y02D10/13

摘要： A method, device, and system to distribute code and data stores between volatile and non-volatile memory are described. In one embodiment, the method includes storing one or more static code segments of a software application in a phase change memory with switch (PCMS) device, storing one or more static data segments of the software application in the PCMS device, and storing one or more volatile data segments of the software application in a volatile memory device. The method then allocates an address mapping table with at least a first address pointer to point to each of the one or more static code segments, at least a second address pointer to point to each of the one or more static data segments, and at least a third address pointer to point to each of the one or more volatile data segments.

摘要翻译： 描述了在易失性和非易失性存储器之间分发代码和数据存储的方法，设备和系统。 在一个实施例中，该方法包括将具有交换机（PCMS）设备的软件应用的一个或多个静态代码段存储在相变存储器中，将该软件应用的一个或多个静态数据段存储在PCMS设备中，并存储一个或多个 在易失性存储器件中软件应用的更易变的数据段。 该方法然后将至少一个第一地址指针的地址映射表分配给一个或多个静态代码段中的每一个，至少第二地址指针指向一个或多个静态数据段中的每一个，并且至少 指向一个或多个易失性数据段中的每一个的第三地址指针。