公开(公告)号：US20050138295A1

公开(公告)日：2005-06-23

申请号：US10743134

申请日：2003-12-23

Applicant: Per Hammarlund ,  Stephan Jourdan ,  Sebastien Hily ,  Aravindh Baktha ,  Hermann Gartler

Inventor： Per Hammarlund ,  Stephan Jourdan ,  Sebastien Hily ,  Aravindh Baktha ,  Hermann Gartler

IPC: G06F9/38 ,  G06F12/00 ,  G06F12/08

CPC classification number: G06F12/0804 ,  G06F9/3824 ,  G06F12/0831

Abstract: Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffer before retirement; and setting a status bit associated with the entry in said store buffer, if the address is in the cache in either exclusive or modified state. The method further includes immediately writing the entry to the first-level cache at or after retirement when the status bit is set; and de-allocating the entry from said store buffer at retirement. The method further may comprise resetting the status bit if the cacheline is allocated over or is evicted from the cache before the store buffer entry attempts to write to the cache.

Abstract translation: 本发明的实施例涉及能够进行有效的高速缓冲存储器管理的存储器管理方案和装置。 该方法包括在执行时将条目写入存储缓冲器; 在退休之前确定该条目的地址是否在与商店缓冲区相关联的一级缓存中; 以及如果所述地址在所述高速缓存中处于独占或修改状态，则设置与所述存储缓冲器中的条目相关联的状态位。 该方法还包括当状态位被置位时，在退出时或之后立即将条目写入到第一级高速缓存; 并在退休时从所述商店缓冲器中分配该条目。 该方法还可以包括如果在存储缓冲器入口试图写入高速缓存之前将高速缓存线分配到高速缓冲存储器上或从高速缓冲存储器中被逐出，则重置状态位。

公开(公告)号：US20050055541A1

公开(公告)日：2005-03-10

申请号：US10658072

申请日：2003-09-08

Applicant: Tor Aamodt ,  Hong Wang ,  Per Hammarlund ,  John Shen ,  Steve Liao ,  Perry Wang

Inventor： Tor Aamodt ,  Hong Wang ,  Per Hammarlund ,  John Shen ,  Steve Liao ,  Perry Wang

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/30101 ,  G06F9/3802 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3859

Abstract: Embodiments of an apparatus, system and method enhance the efficiency of processor resource utilization during instruction prefetching via one or more speculative threads. Renamer logic and a map table are utilized to perform filtering of instructions in a speculative thread instruction stream. The map table includes a yes-a-thing bit to indicate whether the associated physical register's content reflects the value that would be computed by the main thread. A thread progress beacon table is utilized to track relative progress of a main thread and a speculative helper thread. Based upon information in the thread progress beacon table, the main thread may effect termination of a helper thread that is not likely to provide a performance benefit for the main thread.

Abstract translation: 装置，系统和方法的实施例通过一个或多个推测性线程增强在指令预取期间处理器资源利用的效率。 利用重命名逻辑和映射表来对推测性线程指令流中的指令进行滤波。 映射表包括一个肯定事件位，用于指示相关联的物理寄存器的内容是否反映由主线程计算的值。 线程进度信标表用于跟踪主线程和推测式辅助线程的相对进度。 基于线程进度信标表中的信息，主线程可能会影响不太可能为主线程提供性能优势的辅助线程的终止。

公开(公告)号：US06711669B2

公开(公告)日：2004-03-23

申请号：US10339571

申请日：2003-01-10

Applicant: Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

Inventor： Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

IPC: G06F900

CPC classification number: G06F9/30178 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/30167

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract translation: 一种包含存储在存储介质上的指令的物品。 该指令包括存储操作码信号的操作码字段和存储操作数信号的操作数字段。 操作数在存储在操作数字段之前被压缩。

公开(公告)号：US06338132B1

公开(公告)日：2002-01-08

申请号：US09223299

申请日：1998-12-30

Applicant: Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

Inventor： Alan B. Kyker ,  Per Hammarlund ,  Chan Lee ,  Robert F. Krick ,  Hitesh Ahuja ,  William Alexander ,  Joseph Rohlman

IPC: G06F900

CPC classification number: G06F9/30178 ,  G06F9/30156 ,  G06F9/3016 ,  G06F9/30167

Abstract: An article comprising an instruction stored on a storage medium. The instruction includes opcode field storing an opcode signal and an operand field storing an operand signal. The operand is compressed prior to being stored in the operand field.

Abstract translation: 一种包含存储在存储介质上的指令的物品。 该指令包括存储操作码信号的操作码字段和存储操作数信号的操作数字段。 操作数在存储在操作数字段之前被压缩。

公开(公告)号：US10089263B2

公开(公告)日：2018-10-02

申请号：US15118501

申请日：2014-03-24

Applicant: INTEL CORPORATION ,  Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

Inventor： Thiam Wah Loh ,  Gautham N. Chinya ,  Per Hammarlund ,  Reza Fortas ,  Hong Wang ,  Huajin Sun

IPC: G06F13/24

Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time, unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time, the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

公开(公告)号：US20170206083A1

公开(公告)日：2017-07-20

申请号：US15475680

申请日：2017-03-31

Applicant: HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

Inventor： HONG WANG ,  PER HAMMARLUND ,  XIANG ZOU ,  JOHN P. SHEN ,  XINMIN TIAN ,  MILIND GIRKAR ,  PERRY H. WANG ,  PIYUSH N. DESAI

IPC: G06F9/30 ,  G06F12/0875 ,  G06F11/30 ,  G06F9/48 ,  G06F11/34

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

公开(公告)号：US08868887B2

公开(公告)日：2014-10-21

申请号：US10982261

申请日：2004-11-05

Applicant: Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

Inventor： Hong Wang ,  Per Hammarlund ,  Xiang Zou ,  John Shen ,  Xinmin Tian ,  Milind Girkar ,  Perry Wang ,  Piyush Desai

IPC: G06F9/00

CPC classification number: G06F13/24 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3851 ,  G06F9/4843 ,  G06F11/3024 ,  G06F11/348 ,  G06F12/0875 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885 ,  G06F2212/452

Abstract: Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect a condition indicating a low level of progress. The monitor can disrupt processing of a program by transferring to a handler in response to detecting the condition indicating a low level of progress. In another embodiment, thread switch logic may be coupled to a plurality of event monitors which monitor events within the multithreading execution logic. The thread switch logic switches threads based at least partially on a programmable condition of one or more of the performance monitors.

Abstract translation: 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。 在一个实施例中，一种装置包括执行多个指令的执行资源和用于检测指示低水平进展的状况的监视器。 响应于检测到指示低水平进展的状况，监视器可以通过传送到处理程序来中断程序的处理。 在另一个实施例中，线程切换逻辑可以耦合到监视多线程执行逻辑内的事件的多个事件监视器。 线程开关逻辑至少部分地基于一个或多个性能监视器的可编程状态来切换线程。

公开(公告)号：US08762694B1

公开(公告)日：2014-06-24

申请号：US11395884

申请日：2006-03-31

Applicant: Xiang Zou ,  Hong Wang ,  Robert Knight ,  Robert Geva ,  Gautham Chinya ,  Scott Dion Rodgers ,  Chris Newburn ,  Bryant E. Bigbee ,  Per Hammarlund ,  Ittai Anati ,  Jim B. Crossland ,  John P. Shen

Inventor： Xiang Zou ,  Hong Wang ,  Robert Knight ,  Robert Geva ,  Gautham Chinya ,  Scott Dion Rodgers ,  Chris Newburn ,  Bryant E. Bigbee ,  Per Hammarlund ,  Ittai Anati ,  Jim B. Crossland ,  John P. Shen

IPC: G06F9/48

CPC classification number: G06F9/3851 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

Abstract: Method, apparatus, and system for a programmable event-driven yield mechanism. The mechanism may disrupt processing of a program to deliver a yield event. The event may be treated as a fault-like yield event or a trap-like event. For a fault-like yield event, the faulting instruction is canceled before retirement and processor state is not updated before the yield event is delivered. For a trap-like yield event the instruction causing the trap is retired and the yield event is delivered on an interrupt boundary. Multiple pending yield events may be handled according to priority. Other embodiments are also described and claimed.

Abstract translation: 用于可编程事件驱动产出机制的方法，装置和系统。 该机制可能会中断处理程序以传递yield事件。 事件可能被视为类似故障的收益事件或类似陷阱的事件。 对于类似故障的产出事件，在退出之前取消故障指令，并且在发送收益事件之前未更新处理器状态。 对于类似陷阱的收益事件，导致陷阱的指令将被退出，并且收益事件在中断边界上传递。 可以根据优先级处理多个待处理的收益事件。 还描述和要求保护其他实施例。

公开(公告)号：US08719806B2

公开(公告)日：2014-05-06

申请号：US12879898

申请日：2010-09-10

Applicant: Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

Inventor： Hong Wang ,  Tor M. Aamodt ,  Pedro Marcuello ,  Jared W. Stark, IV ,  John P. Shen ,  Antonio Gonzalez ,  Per Hammarlund ,  Gerolf F. Hoflehner ,  Perry H. Wang ,  Steve Shih-wei Liao

IPC: G06F9/45

CPC classification number: G06F9/4843 ,  G06F8/433 ,  G06F9/3009 ,  G06F9/3808 ,  G06F9/3832 ,  G06F9/3842 ,  G06F9/3851

Abstract: The latencies associated with retrieving instruction information for a main thread are decreased through the use of a simultaneous helper thread. The helper thread is a speculative prefetch thread to perform instruction prefetch and/or trace pre-build for the main thread.

Abstract translation: 通过使用同时提供的线程来减少与检索主线程的指令信息相关的延迟。 辅助线程是用于为主线程执行指令预取和/或跟踪预构建的推测性预取线程。

公开(公告)号：US08560781B2

公开(公告)日：2013-10-15

申请号：US13175928

申请日：2011-07-04

Applicant: Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

Inventor： Quinn A. Jacobson ,  Anne Weinberger Bracy ,  Hong Wang ,  John P. Shen ,  Per Hammarlund ,  Matthew C. Merten ,  Suresh Srinivas ,  Kshitij A. Doshi ,  Gautham N. Chinya ,  Bratin Saba ,  Ali-Reza Adl-Tabatabai ,  Gad S. Sheaffer

IPC: G06F12/00

CPC classification number: G06F12/0815 ,  G06F11/3471 ,  G06F11/3648 ,  G06F12/0804 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/0842 ,  G06F12/145 ,  G06F2201/865

Abstract: A technique for using memory attributes to relay information to a program or other agent. More particularly, embodiments of the invention relate to using memory attribute bits to check various memory properties in an efficient manner.

Abstract translation: 一种使用存储器属性将信息中继到程序或其他代理的技术。 更具体地，本发明的实施例涉及使用存储器属性位以有效的方式检查各种存储器特性。