公开(公告)号：US20070246755A1

公开(公告)日：2007-10-25

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US07592233B2

公开(公告)日：2009-09-22

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US07541244B2

公开(公告)日：2009-06-02

申请号：US11491704

申请日：2006-07-24

申请人： Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/336

CPC分类号： H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

公开(公告)号：US20080305593A1

公开(公告)日：2008-12-11

申请号：US11949786

申请日：2007-12-04

申请人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

发明人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

摘要翻译： 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US07446355B2

公开(公告)日：2008-11-04

申请号：US11556170

申请日：2006-11-03

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Pei-Ing Lee ,  Chung-Yuan Lee

IPC分类号： H01L29/76

CPC分类号： H01L29/66553 ,  H01L21/26586 ,  H01L27/10876 ,  H01L29/66621 ,  H01L29/66659

摘要： A method of fabricating self-aligned recess utilizing asymmetric poly spacer is disclosed. A semiconductor substrate having thereon a first pad layer and second pad layer is provided. A plurality of trenches is embedded in a memory array region of the semiconductor substrate. Each of the trenches includes a trench top layer that extrudes from a main surface of the semiconductor substrate. Asymmetric poly spacer is formed on one side of the extruding trench top layer and is used, after oxidized, as a mask for forming a recess in close proximity to the trenches.

摘要翻译： 公开了一种使用不对称聚合间隔物制造自对准凹槽的方法。 提供了其上具有第一焊盘层和第二焊盘层的半导体衬底。 多个沟槽嵌入在半导体衬底的存储器阵列区域中。 每个沟槽包括从半导体衬底的主表面挤出的沟槽顶层。 非对称聚合物间隔物形成在挤出沟槽顶层的一侧上，并且在氧化之后用作用于在靠近沟槽形成凹部的掩模。

公开(公告)号：US07429509B2

公开(公告)日：2008-09-30

申请号：US11145585

申请日：2005-06-06

申请人： Pei-Ing Lee

发明人： Pei-Ing Lee

IPC分类号： H01L21/8242

CPC分类号： H01L27/10888 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/66621 ,  H01L29/7834

摘要： A method for forming a semiconductor device. A substrate is provided, wherein the substrate has recessed gates and deep trench capacitor devices therein. Protrusions of the recessed gates and upper portions of the deep trench capacitor devices are revealed. Spacers are formed on sidewalls of the upper portions and the protrusions. Buried portions of conductive material are formed in spaces between the spacers. The substrate, the spacers and the buried portions to form parallel shallow trenches are patterned to form parallel shallow trenches for defining active regions. A layer of dielectric material is formed in the shallow trenches, wherein some of the buried portions serve as buried contacts.

摘要翻译： 一种形成半导体器件的方法。 提供了一种衬底，其中衬底在其中具有凹入栅极和深沟槽电容器器件。 显露了深沟槽电容器器件的凹入栅极和上部的突出。 间隔件形成在上部和突起的侧壁上。 导电材料的埋入部分形成在间隔件之间的空间中。 图案化衬底，间隔物和形成平行的浅沟槽的掩埋部分以形成用于限定活性区域的平行的浅沟槽。 在浅沟槽中形成介电材料层，其中一些掩埋部分用作掩埋触点。

公开(公告)号：US20070190736A1

公开(公告)日：2007-08-16

申请号：US11616849

申请日：2006-12-27

申请人： An-Hsiung Liu ,  Chiang-Lin Shih ,  Wen-Bin Wu ,  Hui-Min Mao ,  Lin-Chin Su ,  Pei-Ing Lee

发明人： An-Hsiung Liu ,  Chiang-Lin Shih ,  Wen-Bin Wu ,  Hui-Min Mao ,  Lin-Chin Su ,  Pei-Ing Lee

IPC分类号： H01L21/20

CPC分类号： H01L29/66181 ,  G03F7/70633 ,  G03F9/7076 ,  G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L27/1087 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A small-size (w

摘要翻译： 提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于制造需要高精度AA-DT和GC-DT重叠对准的沟槽电容器DRAM器件。 利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并刷新沟槽轮廓，从而提高覆盖对准精度和精度。

公开(公告)号：US06368912B1

公开(公告)日：2002-04-09

申请号：US09733888

申请日：2000-12-08

申请人： Chi-Han Chang ,  Tzu-En He ,  Hsin-Chuan Tsai ,  Pei-Ing Lee

发明人： Chi-Han Chang ,  Tzu-En He ,  Hsin-Chuan Tsai ,  Pei-Ing Lee

IPC分类号： H01L318242

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron. The upper portion of the insulating layer in the alternative approach is also can be replaced by a low-cost sacrificial layer.

摘要翻译： 提供了一种在深沟槽电容器和垂直晶体管之间制造水平隔离结构的方法。 深沟槽电容器位于衬底的深沟槽的底部。 形成绝缘层以通过高密度等离子体化学气相沉积部分地填充深沟槽以及衬底上。 去除深沟槽和衬底的侧壁上的绝缘层，以将深沟槽中的绝缘层转变成隔离结构。 另一种方法是在衬底和深沟槽中形成绝缘层。 然后执行CMP以去除衬底上的绝缘层，并且执行蚀刻以去除深沟槽中的绝缘层的上部。 然后，深沟槽中保留的绝缘层用作深沟槽电容器和垂直晶体管之间的隔离结构。 替代方法中的绝缘层的上部也可以由低成本牺牲层代替。

公开(公告)号：US5834829A

公开(公告)日：1998-11-10

申请号：US706586

申请日：1996-09-05

申请人： Bettina A. Dinkel ,  Pei-Ing Lee ,  Ernest N. Levine

发明人： Bettina A. Dinkel ,  Pei-Ing Lee ,  Ernest N. Levine

IPC分类号： H01L21/301 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/78 ,  H01L23/52 ,  H01L23/544

CPC分类号： H01L21/78 ,  H01L21/768

摘要： An energy relieving, redundant crack stop and the method of producing the same is disclosed. The redundant pattern allows the crack propagating energy that is not absorbed by the first ring of metallization to be absorbed by a second area of metallization and also provides a greater surface area over which the crack producing energy may be spread. The redundant crack stop is produced during the metallization process along with the rest of the wiring of the chip surface and, therefore, no additional production steps are necessary to form the structure.

摘要翻译： 公开了一种能量消除，冗余裂缝停止及其制造方法。 冗余图案允许不被第一金属化环吸收的裂纹传播能量被金属化的第二区域吸收，并且还提供更大的表面积，裂纹产生能量在该表面积上可以扩展。 在金属化处理期间，与芯片表面的其余布线一起产生冗余裂纹停止，因此，不需要额外的制造步骤来形成结构。

公开(公告)号：US20070190712A1

公开(公告)日：2007-08-16

申请号：US11521639

申请日：2006-09-14

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/42376 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

摘要翻译： 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。 杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻沟槽下方的半导体衬底以形成延伸部分。 在沟槽和延伸部分上形成栅极绝缘层。 在沟槽和延伸部分中形成沟槽栅极。