公开(公告)号：US06368912B1

公开(公告)日：2002-04-09

申请号：US09733888

申请日：2000-12-08

申请人： Chi-Han Chang ,  Tzu-En He ,  Hsin-Chuan Tsai ,  Pei-Ing Lee

发明人： Chi-Han Chang ,  Tzu-En He ,  Hsin-Chuan Tsai ,  Pei-Ing Lee

IPC分类号： H01L318242

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： A method of fabricating a horizontal isolation structure between a deep trench capacitor and a vertical transistor thereon is provided. A deep trench capacitor is in the bottom of a deep trench of a substrate. An insulating layer is formed to partially fill the deep trench and also on the substrate by high-density plasma chemical vapor deposition. The insulating layer on the sidewall of the deep trench and on the substrate is removed to transform the insulating layer in the deep trench to an isolation structure. An alternative approach is to form an insulating layer on the substrate and in the deep trench. Then a CMP is performed to remove the insulating layer on the substrate and an etching back is performed to remove the upper portion of the insulating layer in the deep trench. Then the remained insulating layer in the deep trench is served as an isolation structure between the deep trench capacitor and a vertical transistor thereron. The upper portion of the insulating layer in the alternative approach is also can be replaced by a low-cost sacrificial layer.

摘要翻译： 提供了一种在深沟槽电容器和垂直晶体管之间制造水平隔离结构的方法。 深沟槽电容器位于衬底的深沟槽的底部。 形成绝缘层以通过高密度等离子体化学气相沉积部分地填充深沟槽以及衬底上。 去除深沟槽和衬底的侧壁上的绝缘层，以将深沟槽中的绝缘层转变成隔离结构。 另一种方法是在衬底和深沟槽中形成绝缘层。 然后执行CMP以去除衬底上的绝缘层，并且执行蚀刻以去除深沟槽中的绝缘层的上部。 然后，深沟槽中保留的绝缘层用作深沟槽电容器和垂直晶体管之间的隔离结构。 替代方法中的绝缘层的上部也可以由低成本牺牲层代替。

公开(公告)号：US06448150B1

公开(公告)日：2002-09-10

申请号：US09055254

申请日：1998-04-06

申请人： Hsin-Chuan Tsai ,  Pei-Ing Lee

发明人： Hsin-Chuan Tsai ,  Pei-Ing Lee

IPC分类号： H01L2176

CPC分类号： H01L21/76229 ,  H01L21/31053 ,  H01L21/31055

摘要： A method for forming shallow trench isolation in an integrated circuit is introduced. Firstly, the first silicon oxide layer and a silicon nitride layer are formed subsequently on the silicon substrate. Then lithography and etching are used to open a shallow trench. Then thermal oxidation is performed. The following step is to form the shallow trench isolation by forming the second silicon oxide with high density plasma enhanced chemical vapor deposition. Then an organic spin-on-glass is coated and low temperature baking is performed. After that, partial etching back is performed to remove spin-on-glass outside the shallow trench. This etching recipe has high selectivity between the second silicon oxide layer to spin-on-glass. Then curing at temperature above 800° C. and etching back are performed with silicon nitride as end point.

摘要翻译： 介绍了一种在集成电路中形成浅沟槽隔离的方法。 首先，在硅衬底上随后形成第一氧化硅层和氮化硅层。 然后使用光刻和蚀刻来打开浅沟槽。 然后进行热氧化。 以下步骤是通过用高密度等离子体增强化学气相沉积形成第二氧化硅来形成浅沟槽隔离。 然后涂覆有机旋涂玻璃并进行低温烘烤。 之后，进行部分蚀刻以去除浅沟槽外的旋涂玻璃。 该蚀刻配方在第二氧化硅层与旋涂玻璃之间具有高选择性。 然后在高于800℃的温度下固化，并且用氮化硅作为终点进行蚀刻。

公开(公告)号：US07932555B2

公开(公告)日：2011-04-26

申请号：US11949788

申请日：2007-12-04

申请人： Pei-Ing Lee ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Shian-Jyh Lin

IPC分类号： H01L29/66

CPC分类号： H01L27/1087 ,  H01L27/10841

摘要： A transistor structure includes a gate trench. The gate trench includes a bottle-shape bottom. The bottle-shape bottom includes a first conductive material wider than its top. The top includes a second material in a substrate, a gate structure on the gate trench and electrically connected to the first conductive material, a source/drain doping region adjacent to the gate trench and a gate channel between the source/drain doping region.

摘要翻译： 晶体管结构包括栅极沟槽。 栅极沟槽包括瓶形底部。 瓶形底部包括比其顶部更宽的第一导电材料。 顶部包括衬底中的第二材料，栅极沟槽上的栅极结构和电连接到第一导电材料，与栅极沟槽相邻的源极/漏极掺杂区域和源极/漏极掺杂区域之间的栅极沟道。

公开(公告)号：US07682902B2

公开(公告)日：2010-03-23

申请号：US11949786

申请日：2007-12-04

申请人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

发明人： Ching-Nan Hsiao ,  Pei-Ing Lee ,  Ming-Cheng Chang ,  Chung-Lin Huang ,  Hsi-Hua Chang ,  Chih-Hsiang Wu

IPC分类号： H01L21/336

CPC分类号： H01L27/11534 ,  H01L21/84 ,  H01L27/11526 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7887

摘要： A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

摘要翻译： 本发明公开的存储器结构的特征在于控制栅极和位于凹槽中的浮栅。 一种制造存储器结构的方法包括以下步骤：首先提供具有第一凹槽的衬底。 然后，在第一凹槽上形成第一栅极电介质层。 第一导电层形成在第一栅极介电层上。 之后，蚀刻第一导电层以形成用作第一凹槽的侧壁上的浮动栅极的间隔物。 在第一凹槽的底部形成第二凹槽。 在间隔物的表面，第二凹槽的侧壁和底部上形成栅极间电介质层。 形成为填充第一和第二凹槽的第二导电层。

公开(公告)号：US20080135907A1

公开(公告)日：2008-06-12

申请号：US12021969

申请日：2008-01-29

申请人： Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L27/108

CPC分类号： H01L29/7834 ,  H01L27/10876 ,  H01L29/42368 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a first trench having a first depth using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the first trench to form a doped region. The doped region and the semiconductor substrate underlying the first trench are etched to form a second trench having a second depth greater than the first depth, wherein the second trench has a sidewall and a bottom. A gate insulating layer is formed on the sidewall and the bottom of the second trench. A trench gate is formed in the second trench.

摘要翻译： 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 蚀刻半导体衬底以形成具有第一深度的第一沟槽，使用沟槽蚀刻掩模作为屏蔽。 杂质通过第一沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻第一沟槽下面的掺杂区域和半导体衬底以形成具有大于第一深度的第二深度的第二沟槽，其中第二沟槽具有侧壁和底部。 栅极绝缘层形成在第二沟槽的侧壁和底部上。 沟槽栅极形成在第二沟槽中。

公开(公告)号：US20080009112A1

公开(公告)日：2008-01-10

申请号：US11858703

申请日：2007-09-20

申请人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

发明人： Pei-Ing Lee ,  Chung-Yuan Lee ,  Chien-Li Cheng

IPC分类号： H01L21/8242

CPC分类号： H01L29/66621 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/1087 ,  H01L27/10876

摘要： A method for forming a semiconductor memory device with a recessed gate is disclosed. A substrate with a pad layer thereon is provided. The pad layer and the substrate are patterned to form at least two trenches. A deep trench capacitor is formed in each trench. A protrusion is formed on each deep trench capacitor, wherein a top surface level of each protrusion is higher than that of the pad layer. Spacers are formed on sidewalls of the protrusions, and the pad layer and the substrate are etched using the spacers and the protrusions as a mask to form a recess. A recessed gate is formed in the recess.

摘要翻译： 公开了一种用于形成具有凹入栅极的半导体存储器件的方法。 提供其上具有垫层的衬底。 图案化衬垫层和衬底以形成至少两个沟槽。 在每个沟槽中形成深沟槽电容器。 在每个深沟槽电容器上形成突起，其中每个突起的顶表面水平高于焊盘层的顶表面高度。 间隔件形成在突起的侧壁上，并且使用间隔件和突起作为掩模来蚀刻衬垫层和衬底以形成凹部。 在凹部中形成凹槽。

公开(公告)号：US20070246755A1

公开(公告)日：2007-10-25

申请号：US11696163

申请日：2007-04-03

申请人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

发明人： Pei-Ing Lee ,  Chien-Li Cheng ,  Shian-Jyh Lin

IPC分类号： H01L29/76 ,  H01L21/8234

CPC分类号： H01L27/10861 ,  H01L27/0629 ,  H01L27/10876

摘要： A method of fabricating self-aligned gate trench utilizing TTO poly spacer is disclosed. A semiconductor substrate having thereon a pad oxide layer and pad nitride layer is provided. A plurality of trench capacitors are embedded in a memory array region of the semiconductor substrate. Each of the trench capacitors has a trench top oxide (TTO) that extrudes from a main surface of the semiconductor substrate. Poly spacers are formed on two opposite sides of the extruding TTO and are used, after oxidized, as an etching hard mask for etching a recessed gate trench in close proximity to the trench capacitor.

摘要翻译： 公开了一种使用TTO多隔离件制造自对准栅极沟槽的方法。 提供其上具有衬垫氧化物层和衬垫氮化物层的半导体衬底。 多个沟槽电容器嵌入在半导体衬底的存储器阵列区域中。 每个沟槽电容器具有从半导体衬底的主表面挤出的沟槽顶部氧化物（TTO）。 聚合物间隔物形成在挤出TTO的两个相对侧上，并且在氧化后用作蚀刻硬掩模，用于蚀刻紧邻沟槽电容器的凹陷栅极沟槽。

公开(公告)号：US20070190712A1

公开(公告)日：2007-08-16

申请号：US11521639

申请日：2006-09-14

申请人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

发明人： Shian-Jyh Lin ,  Chien-Li Cheng ,  Chung-Yuan Lee ,  Jeng-Ping Lin ,  Pei-Ing Lee

IPC分类号： H01L21/8234

CPC分类号： H01L29/42376 ,  H01L29/66621

摘要： A method of fabricating a semiconductor device having a trench gate is provided. First, a semiconductor substrate having a trench etch mask thereon is provided. The semiconductor substrate is etched to form a trench having a sidewall and a bottom using the trench etch mask as a shield. Impurities are doped into the semiconductor substrate through the trench to form a doped region. The semiconductor substrate underlying the trench is etched to form an extended portion. A gate insulating layer is formed on the trench and the extended portion. A trench gate is formed in the trench and the extended portion.

摘要翻译： 提供一种制造具有沟槽栅极的半导体器件的方法。 首先，提供其上具有沟槽蚀刻掩模的半导体衬底。 使用沟槽蚀刻掩模作为屏蔽，蚀刻半导体衬底以形成具有侧壁和底部的沟槽。 杂质通过沟槽掺杂到半导体衬底中以形成掺杂区域。 蚀刻沟槽下方的半导体衬底以形成延伸部分。 在沟槽和延伸部分上形成栅极绝缘层。 在沟槽和延伸部分中形成沟槽栅极。

公开(公告)号：US20060270149A1

公开(公告)日：2006-11-30

申请号：US11141656

申请日：2005-05-31

申请人： Pei-Ing Lee

发明人： Pei-Ing Lee

IPC分类号： H01L21/336 ,  H01L21/8242

CPC分类号： H01L27/10876 ,  H01L27/10823 ,  H01L27/10829 ,  H01L27/10891

摘要： A method for forming a semiconductor device. A substrate, having a plurality of deep trench capacitors therein, is provided wherein upper portions of the deep trench capacitor devices are revealed. Spacers on sidewalls of the upper portions of the deep trench capacitors are formed to form a predetermined region surrounded by the deep trench capacitor devices. The predetermined region of the substrate is etched using the spacers and the upper portions of the deep trench capacitors serve as a mask to form a recess, and a recessed gate is formed in the recess.

摘要翻译： 一种形成半导体器件的方法。 提供了其中具有多个深沟槽电容器的衬底，其中露出了深沟槽电容器器件的上部。 形成深沟槽电容器的上部侧壁上的间隔，以形成由深沟槽电容器器件包围的预定区域。 使用间隔物蚀刻衬底的预定区域，并且深沟槽电容器的上部用作掩模以形成凹部，并且在凹部中形成凹入栅极。

公开(公告)号：US20060234440A1

公开(公告)日：2006-10-19

申请号：US11160683

申请日：2005-07-05

申请人： Yuan-Hsun WU ,  An-Hsiung Liu ,  Chiang-Lin Shih ,  Pei-Ing Lee ,  Hui-Min Mao ,  Lin-Chin Su

发明人： Yuan-Hsun WU ,  An-Hsiung Liu ,  Chiang-Lin Shih ,  Pei-Ing Lee ,  Hui-Min Mao ,  Lin-Chin Su

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： G03F9/7084 ,  G03F7/70633 ,  G03F9/708 ,  H01L23/544 ,  H01L27/1087 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A small-size (w

摘要翻译： 提出了与“k1工艺”结合的小尺寸（w <0.5微米）对准标记，其特别适用于需要高精度AA-DT对准的沟槽电容器DRAM器件的制造。 利用“k1工艺”来蚀刻散布在对准标记沟槽中的多晶硅，并且在AA图案转印之前刷新沟槽轮廓，从而提高晶片对准精度和精度。