公开(公告)号：US20060237716A1

公开(公告)日：2006-10-26

申请号：US11392238

申请日：2006-03-29

Applicant: Recai Sezi ,  Andreas Walter ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann

Inventor： Recai Sezi ,  Andreas Walter ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann

IPC: H01L29/08 ,  H01L51/00 ,  C07D409/04 ,  H01L21/20

CPC classification number: H01L51/0595 ,  B82Y10/00 ,  H01L51/0051

Abstract: The present invention relates to compositions for storage applications, relates to a memory cell which comprises the abovementioned composition and two electrodes and furthermore relates to a process for the production of microelectronic components and the use of the composition according to the invention in the production of these microelectronic components.

Abstract translation: 本发明涉及用于存储应用的组合物，涉及一种包含上述组合物和两个电极的存储单元，此外还涉及一种用于生产微电子组件的方法以及根据本发明的组合物在制备这些组合物中的用途 微电子元件。

公开(公告)号：US09059083B2

公开(公告)日：2015-06-16

申请号：US11855712

申请日：2007-09-14

Applicant: Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

Inventor： Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

IPC: H01L23/12 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L23/5389 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/4821 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/00 ,  H05K3/4661

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Abstract translation: 公开了一种半导体器件。 一个实施例包括载体，附接到载体的半导体芯片，具有第一厚度并沉积在半导体芯片和载体上的第一导线和具有第二厚度并沉积在半导体芯片上的第二导线， 载体 第一厚度小于第二厚度。

公开(公告)号：US07955901B2

公开(公告)日：2011-06-07

申请号：US11867329

申请日：2007-10-04

Applicant: Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann ,  Alvin Wee Beng Tatt ,  Soon Lock Goh ,  Joachim Mahler ,  Boris Plikat ,  Reimund Engl

Inventor： Henrik Ewe ,  Stefan Landau ,  Klaus Schiess ,  Robert Bergmann ,  Alvin Wee Beng Tatt ,  Soon Lock Goh ,  Joachim Mahler ,  Boris Plikat ,  Reimund Engl

IPC: H01L23/48

CPC classification number: H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/24 ,  H01L24/80 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32245 ,  H01L2224/76155 ,  H01L2224/82007 ,  H01L2224/82039 ,  H01L2224/82102 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/00

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract translation: 公开了一种具有表面安装平坦的外部接触区域的功率半导体模块的制造方法。 至少一个功率半导体芯片由其后侧固定在漏极外部触点上。 绝缘层覆盖半导体芯片的侧边缘上方的顶侧，只要内壳平面离开半导体芯片的顶侧上的源极和栅极接触区域，并且还部分地释放出半导体芯片的顶侧 相应的外部联系人。

公开(公告)号：US07675146B2

公开(公告)日：2010-03-09

申请号：US11851977

申请日：2007-09-07

Applicant: Reimund Engl ,  Michael Bauer

Inventor： Reimund Engl ,  Michael Bauer

IPC: H01L23/495

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier.

Abstract translation: 半导体器件包括具有第一面和相对的第二面的引线框架，第一面的一部分限定管芯焊盘，沉积在管芯焊盘的至少一部分上的扩散阻挡层以及耦合到扩散层的至少一个芯片 屏障。

公开(公告)号：US20090072379A1

公开(公告)日：2009-03-19

申请号：US11855712

申请日：2007-09-14

Applicant: Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

Inventor： Henrik Ewe ,  Joachim Mahler ,  Manfred Mengel ,  Reimund Engl ,  Josef Hoeglauer ,  Jochen Dangelmaier

IPC: H01L23/12 ,  H01L21/00

CPC classification number: H01L23/5389 ,  H01L21/02282 ,  H01L21/02288 ,  H01L21/288 ,  H01L21/31105 ,  H01L21/4821 ,  H01L21/6835 ,  H01L21/76801 ,  H01L21/76871 ,  H01L21/76877 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49534 ,  H01L23/49541 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/24 ,  H01L24/25 ,  H01L24/82 ,  H01L2221/68345 ,  H01L2224/24011 ,  H01L2224/2402 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24145 ,  H01L2224/24226 ,  H01L2224/24246 ,  H01L2224/24998 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/76155 ,  H01L2224/82001 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82102 ,  H01L2225/06568 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/00 ,  H05K3/4661

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.

Abstract translation: 公开了一种半导体器件。 一个实施例包括载体，附接到载体的半导体芯片，具有第一厚度并沉积在半导体芯片和载体上的第一导线和具有第二厚度并沉积在半导体芯片上的第二导线， 载体 第一厚度小于第二厚度。

公开(公告)号：US20090065914A1

公开(公告)日：2009-03-12

申请号：US11851977

申请日：2007-09-07

Applicant: Reimund Engl ,  Michael Bauer

Inventor： Reimund Engl ,  Michael Bauer

IPC: H01L23/495 ,  H01L21/00

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/49575 ,  H01L23/49582 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device includes a leadframe having a first face and an opposing second face, a portion of the first face defining a die pad, a diffusion barrier deposited on at least a portion of the die pad, and at least one chip coupled to the diffusion barrier.

Abstract translation: 半导体器件包括具有第一面和相对的第二面的引线框架，第一面的一部分限定管芯焊盘，沉积在管芯焊盘的至少一部分上的扩散阻挡层以及耦合到扩散层的至少一个芯片 屏障。

公开(公告)号：US07417247B2

公开(公告)日：2008-08-26

申请号：US11092968

申请日：2005-03-30

Applicant: Günter Schmid ,  Hagen Klauk ,  Marcus Halik ,  Reimund Engl ,  Andreas Walter

Inventor： Günter Schmid ,  Hagen Klauk ,  Marcus Halik ,  Reimund Engl ,  Andreas Walter

IPC: H01L51/30 ,  C08F8/02

CPC classification number: G11C13/0014 ,  B82Y10/00 ,  C08G61/02 ,  G11C13/0016 ,  G11C2213/72 ,  H01L51/0035 ,  H01L51/004 ,  H01L51/005 ,  H01L51/0591

Abstract: Polymers are described which exhibit a resistive hysteresis effect. The polymers include a polymer backbone to which pentaarylcyclopentadienyl radicals are bonded as side groups. A resistive memory element is formed that includes the polymer as a storage medium. By applying a voltage, the memory element can be switched between a nonconductive and a conductive state.

Abstract translation: 描述了表现出电阻滞后效应的聚合物。 聚合物包括作为侧基键合五芳基环戊二烯基的聚合物主链。 形成包含作为存储介质的聚合物的电阻式存储元件。 通过施加电压，可以在非导通状态和导通状态之间切换存储​​元件。

公开(公告)号：US20080142774A1

公开(公告)日：2008-06-19

申请号：US11572950

申请日：2005-07-20

Applicant: Andreas Walter ,  Thomas Weitz ,  Reimund Engl ,  Recai Sezi ,  Anna Maltenberger ,  Joerg Schumann

Inventor： Andreas Walter ,  Thomas Weitz ,  Reimund Engl ,  Recai Sezi ,  Anna Maltenberger ,  Joerg Schumann

IPC: H01L45/00 ,  H01L51/40 ,  H01L51/30

CPC classification number: H01L27/285 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L51/0035 ,  H01L51/0051 ,  H01L51/0074 ,  H01L51/0591 ,  H01L51/0595

Abstract: An integrated circuit having resistive memory is disclosed. In one embodiment, the memory includes novel memory cells which have two electrodes and a layer arranged in between and including an active material which contains [1,2]dithiolo[4,3-[c]-1,2-dithiol-3,6-dithione, (2,4,7-trinitro-9-fluorenylidene)malonodinitrile and a polymer are disclosed. In one embodiment, a process for the production of the cells according to the invention is provided, as well as the novel use of a composition which can be used as active material for the memory cells.

Abstract translation: 公开了一种具有电阻性存储器的集成电路。 在一个实施例中，存储器包括新颖的存储单元，其具有两个电极和布置在其中并且包括含有[1,2]二硫基[4,3-c] -1,2-二硫醇-3的活性材料的层， （2,4,7-三硝基-9-亚芴基）丙二腈和聚合物。 在一个实施方案中，提供了根据本发明的细胞的制备方法，以及可用作记忆细胞的活性物质的组合物的新用途。

公开(公告)号：US07211856B2

公开(公告)日：2007-05-01

申请号：US11041760

申请日：2005-01-24

Applicant: Recai Sezi ,  Andreas Walter ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann ,  Thomas Weitz

Inventor： Recai Sezi ,  Andreas Walter ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann ,  Thomas Weitz

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L51/0051 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L27/285 ,  H01L51/005 ,  H01L51/0595

Abstract: Memory cells having two electrodes and a layer arranged in between and including an active material which contains hexakisbenzylthiobenzene, dichlorodicyano-p-benzoquinone and optionally a polymer are provided. Furthermore, a process for the production of the cells according to the invention is provided, as well as the novel use of a composition which can be used as active material for the memory cells.

Abstract translation: 提供具有两个电极和布置在其中并包含含有六苯基苯硫基苯，二氯二氰基对苯醌和任选的聚合物的活性材料的层的记忆单元。 此外，提供了根据本发明的细胞的制备方法，以及可用作记忆单元的活性材料的组合物的新用途。

公开(公告)号：US20050179033A1

公开(公告)日：2005-08-18

申请号：US11044762

申请日：2005-01-27

Applicant: Andreas Walter ,  Recai Sezi ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann ,  Thomas Weitz

Inventor： Andreas Walter ,  Recai Sezi ,  Reimund Engl ,  Anna Maltenberger ,  Joerg Schumann ,  Thomas Weitz

IPC: C07C211/50 ,  C07D345/00 ,  G11C11/21 ,  G11C13/00 ,  G11C13/02 ,  H01L27/24 ,  H01L27/28 ,  H01L29/08 ,  H01L35/24 ,  H01L51/30

CPC classification number: H01L51/0595 ,  B82Y10/00 ,  G11C13/0014 ,  G11C13/0016 ,  H01L27/285 ,  H01L51/0051

Abstract: A memory cell is provided which comprises two electrodes and a layer arranged in between and comprising an active material comprising (a) a compound selected from the group consisting of in which R1 and R4, independently of one another, may have the following meaning: —H, -alkyl, -aryl, -heteroaryl, —O-alkyl, —O-aryl, —O-heteroaryl, —SH, —S-alkyl, —S-aryl, —S-heteroaryl, —CO-alkyl, —CO-aryl, —CO-heteroaryl, —CS-alkyl, —CS-aryl, —CS-heteroaryl, -halogen, —CN and/or —NO2, in which R1 and R2, R2 and R3, R3 and R4 together may form a ring, (b) a compound of the general formula II: in which R5 to R7, independently of one another, may have the following meaning: —H, -alkyl, -aryl, -heteroaryl, —O-alkyl, —O-aryl, —O-heteroaryl, —NH2, —N(alkyl)2, —N(aryl)2, —N(heteroaryl)2, —SH, —S-alkyl, —S-aryl, —S-heteroaryl, —CO-alkyl, —CO-aryl, —CO-heteroaryl, —CS-alkyl, —CS-aryl, —CS-heteroaryl, -halogen, —CN and/or —NO2, in which R5 and R6 or R7 and R8 together may form a ring, and optionally (c) a polymer. A method for the production of the cells according to the invention and the novel use of a composition which can be used as active material for the memory cells are furthermore provided.

Abstract translation: 提供了一种存储单元，其包括两个电极和布置在其间并包含活性材料的层，所述活性材料包含（a）选自下组的化合物：其中R 1和R 2， 可以具有以下含义：-H， - 烷基， - 芳基， - 杂芳基，-O-烷基，-O-芳基， - O-杂芳基，-SH - ， - S-烷基， -S-芳基，-S-杂芳基，-CO-烷基，-CO-芳基，-CO-杂芳基，-CS-烷基，-CS-芳基，-CS-杂芳基， - 卤素，-CN和/或-NO 其中R 1和R 2，R 2和R 3， R 3和R 4一起可以形成环，（b）通式II的化合物：其中R 5至R 可以具有如下含义：-H， - 烷基， - 芳基， - 杂芳基， - - - 烷基，-O-芳基， - O-杂芳基， N（烷基）2，-N（芳基）2 N，-N（杂芳基）2， -SH，-S-烷基，-S-芳基，-S-杂芳基，-CO-烷基，-CO-芳基 ，-CO-杂芳基，-CS-烷基，-CS-芳基，-CS-杂芳基， - 卤素，-CN和/或-NO 2，其中R 5 和R 6或R 7和R 8一起可以形成环，和任选地（c）聚合物。 此外还提供了用于生产根据本发明的电池的方法和可用作存储器电池的活性材料的组合物的新用途。