公开(公告)号：US20030214351A1

公开(公告)日：2003-11-20

申请号：US10356650

申请日：2003-01-31

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Tapas Nandy ,  Kirtiman Singh Rathore

IPC: H03F001/02 ,  H03F003/45

CPC classification number: H03F3/45753

Abstract: A method for reducing offset voltage in an operational amplifier without the need for switched-capacitors, includes introducing a tapped resistor chain between the common connected terminals of the transistors of the input differential pair of the operational amplifier and connecting the tail current source/sink of the differential amplifier to a selected tap of the resistor chain. The invention further provides an improved operational amplifier in accordance with the above method.

Abstract translation: 一种用于减少运算放大器中的失调电压而不需要开关电容的方法包括在运算放大器的输入差分对的晶体管的公共连接端子之间引入分接电阻器链，并将尾电流源/ 差分放大器到电阻链的选定分接头。 本发明还提供了一种根据上述方法的改进的运算放大器。

公开(公告)号：US20030086518A1

公开(公告)日：2003-05-08

申请号：US10285329

申请日：2002-10-30

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kalyana Chakravarthy

IPC: H04L007/02 ,  H03D003/24

CPC classification number: H04N21/4305 ,  H03L7/0992 ,  H03L7/181

Abstract: A method and an improved apparatus for clock recovery from data streams containing embedded reference clock values controlled clock source means includes of a controllable digital fractional divider means receiving a control value from digital comparator means and a clock input from a digital clock synthesizer means driven by a fixed oscillator means.

Abstract translation: 一种用于从包含嵌入式参考时钟值的数据流中恢复时钟的方法和改进装置，所述控制时钟源装置包括从数字比较器装置接收控制值的可控数字分数器装置和由数字比较器装置驱动的数字时钟合成器装置的时钟输入 固定振荡器装置。

公开(公告)号：US20030076137A1

公开(公告)日：2003-04-24

申请号：US10269838

申请日：2002-10-10

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Kalyana Chakravarthy

IPC: H03K023/50

CPC classification number: H03L7/1976 ,  H03K23/68

Abstract: An improved fractional divider that comprises an integer value storage means containing the integer part of the division value nullKnull connected to the input of a programmable counter means that is configured for a count value of nullKnull or nullKnull1null depending upon the state of a count control signal and generates the output signal as well a terminal count signal which is connected to an enable input of a fractional accumulator means that produces the count control signal on an addition overflow and has a first input connected to its result output and a second input connected to the output of a fractional value storage means, containing the fractional part of the divider value.

Abstract translation: 一种改进的分数分割器，其包括整数值存储装置，其包含连接到可编程计数器装置的输入的除法值“K”的整数部分，该可编程计数器装置被配置用于计数值“K”或“K + 1”，这取决于 计数控制信号的状态，并且产生输出信号以及终端计数信号，该终端计数信号连接到分数累加器装置的使能输入，该分数累加器装置在加法溢出时产生计数控制信号，并且具有连接到其结果输出的第一输入 以及连接到分数值存储装置的输出的第二输入，其包含分频值的小数部分。

公开(公告)号：US09245606B2

公开(公告)日：2016-01-26

申请号：US13682592

申请日：2012-11-20

Applicant: STMicroelectronics PVT LTD. ,  STMicroelectronics S.r.l.

Inventor： Danilo Rimondi ,  Carolina Selva ,  Ashish Kumar

IPC: G11C11/00 ,  G11C11/14 ,  G11C11/413 ,  G11C7/20 ,  G11C7/22 ,  G11C29/12 ,  G11C29/24 ,  G11C11/41

CPC classification number: G11C11/00 ,  G11C7/20 ,  G11C7/227 ,  G11C11/41 ,  G11C11/413 ,  G11C29/12015 ,  G11C29/24

Abstract: A static random access memory (SRAM) device includes a memory array of a plurality of memory cells, a controller that receives an external clock signal formed by a succession of external pulses and generates an internal clock signal formed by a succession of internal pulses, and a driving circuit that receives the internal clock signal. The controller is operable in a first mode, wherein the controller generates, for each external pulse, a corresponding internal pulse and the controller controls the driving circuit so that the driving circuitry carries out one access to the memory array for each internal pulse. The controller is further operable in a second mode, wherein the controller generates, for each external pulse, a pair of internal pulses, and the controller controls the driving circuitry so that, for each pair of internal pulses, the driving circuitry writes a first data item in a set of memory cells, and then reads the set of memory cells, so as to acquire a second data item.

Abstract translation: 静态随机存取存储器（SRAM）装置包括多个存储单元的存储器阵列，一个接收由一连串外部脉冲形成的外部时钟信号并产生一系列内部脉冲形成的内部时钟信号的控制器，以及 一个接收内部时钟信号的驱动电路。 控制器可在第一模式下操作，其中控制器针对每个外部脉冲产生相应的内部脉冲，并且控制器控制驱动电路，使得驱动电路对每个内部脉冲执行对存储器阵列的一次访问。 控制器还可在第二模式中操作，其中控制器针对每个外部脉冲产生一对内部脉冲，并且控制器控制驱动电路，使得对于每对内部脉冲，驱动电路写入第一数据 项目，然后读取该组存储器单元，以便获取第二数据项。

公开(公告)号：US08996943B2

公开(公告)日：2015-03-31

申请号：US13722594

申请日：2012-12-20

Applicant: STMicroelectronics Pvt. Ltd. ,  STMicroelectronics S.r.I.

Inventor： Nicolas Bernard Grossier ,  Sabyasachi Das ,  V Srinivasan

IPC: G06F11/00 ,  G05F1/56 ,  G01R31/00 ,  G01R31/319 ,  G05F1/10

CPC classification number: G05F1/56 ,  G01R31/00 ,  G01R31/31924 ,  G05F1/10

Abstract: A Voltage regulator includes a first input terminal configured to receive an input supply voltage, includes a second input terminal configured to receive a regulated output supply voltage as a function of the input supply voltage or to receive a test supply voltage and comprises a power transistor including an input terminal configured to receive the input supply voltage and including an output terminal configured to generate the regulated output supply voltage. The Voltage regulator is configured, during a start-up phase of a test operation mode, to receive a control signal equal to the input supply voltage, is configured to receive the input supply voltage having a substantially increasing trend, detect that the input supply voltage is equal to a first voltage threshold and generate, as a function of the detected signal and of the control signal, a by-pass signal having a transition from a first logic value to a second logic value for indicating a by-pass status of the Voltage regulator, and is configured to receive the by-pass signal having the second logic value and open the power transistor. The second input terminal is configured, during the test operation mode, to receive the test supply voltage having a test value different from a nominal value of the regulated output supply voltage.

Abstract translation: 电压调节器包括被配置为接收输入电源电压的第一输入端子，包括被配置为接收作为输入电源电压的函数的调节输出电源电压或者接收测试电源电压的第二输入端子，并且包括功率晶体管，包括 输入端子，被配置为接收所述输入电源电压并且包括被配置为产生所述稳定的输出电源电压的输出端子。 电压调节器在测试操作模式的启动阶段被配置为接收等于输入电源电压的控制信号，被配置为接收具有基本上增加的趋势的输入电源电压，检测输入电源电压 等于第一电压阈值，并且根据所检测的信号和控制信号产生具有从第一逻辑值到第二逻辑值的转变的旁路信号，用于指示所述第一电压阈值的旁路状态 电压调节器，并且被配置为接收具有第二逻辑值的旁路信号并且打开功率晶体管。 在测试操作模式期间，第二输入端被配置为接收具有与调节输出电源电压的标称值不同的测试值的测试电源电压。

公开(公告)号：US20140184912A1

公开(公告)日：2014-07-03

申请号：US13998719

申请日：2013-11-26

Applicant: STMicroelectronics Pvt Ltd.

Inventor： RajeshSidana Omprakash

IPC: H04N5/445

CPC classification number: G09G5/003 ,  G06F3/0481 ,  G06F2203/04803 ,  G06K9/325 ,  G06T2207/10016 ,  G06T2207/20104 ,  G09G5/14 ,  G09G2320/0613 ,  G09G2320/0686 ,  G09G2320/103 ,  G09G2360/16 ,  H04N5/144 ,  H04N21/4316

Abstract: A video window detector includes a region characteristic determiner to generate at least one characteristic value for at least one region of a display output; a characteristic map generator to generate an image map from the at least one characteristic value for at least one region of the display output; and a window detector to detect at least one video window dependent on the image map.

Abstract translation: 视频窗口检测器包括：区域特征确定器，用于为显示输出的至少一个区域生成至少一个特征值; 特征图生成器，用于根据所述显示输出的至少一个区域的所述至少一个特征值生成图像映射; 以及窗口检测器，用于根据图像映射检测至少一个视频窗口。

公开(公告)号：US20140036564A1

公开(公告)日：2014-02-06

申请号：US13954908

申请日：2013-07-30

Applicant: STMicroelectronics PVT LTD ,  STMicroelectronics S.r.l.

Inventor： Fabio DE SANTIS ,  Marco PASOTTI ,  Abhishek LAL

IPC: G11C5/02

CPC classification number: G11C5/02 ,  G11C5/025 ,  G11C7/18 ,  G11C8/12 ,  G11C16/00 ,  G11C16/08 ,  G11C16/24

Abstract: An embodiment of a non-volatile memory device includes: a memory array, having a plurality of non-volatile logic memory cells arranged in at least one logic row, the logic row including a first row and a second row sharing a common control line; and a plurality of bit lines. Each logic memory cell has a direct memory cell, for storing a logic value, and a complementary memory cell, for storing a second logic value, which is complementary to the first logic value in the corresponding direct memory cell. The direct memory cell and the complementary memory cell of each logic memory cell are coupled to respective separate bit lines and are placed one in the first row and the other in the second row of the respective logic row.

Abstract translation: 非易失性存储器件的实施例包括：存储器阵列，其具有布置在至少一个逻辑行中的多个非易失性逻辑存储器单元，所述逻辑行包括共享公共控制线的第一行和第二行; 和多个位线。 每个逻辑存储器单元具有用于存储逻辑值的直接存储单元和用于存储第二逻辑值的互补存储器单元，该第二逻辑值与对应的直接存储器单元中的第一逻辑值互补。 每个逻辑存储单元的直接存储单元和互补存储单元被耦合到相应的单独的位线，并且被放置在相应的逻辑行的第二行中的第一行而另一个中。

公开(公告)号：US20040178778A1

公开(公告)日：2004-09-16

申请号：US10731884

申请日：2003-12-09

Applicant: STMicroelectronics PVT. LTD.

Inventor： Nitin Bansal

IPC: G05F001/40

CPC classification number: G05F1/575

Abstract: An integrated Low Dropout (LDO) linear voltage regulator provides improved current limiting. A differential voltage amplifier compares an output voltage to reference voltage and controls a pass transistor to make the output voltage substantially match the reference voltage. This is accomplished by sensing the output voltage of the voltage regulator for application to a first input of the differential amplifier and coupling a second input of the differential amplifier to the reference voltage. A current sense transistor utilizes current mirroring techniques to sense the current passing through the pass transistor to the output. This sensed current is compared to a reference current. The result of that comparison is fed back to the differential voltage amplifier to in a manner that increases the apparently sensed output voltage in situations where the sensed current exceeds the reference current.

Abstract translation: 集成的低压差（LDO）线性稳压器提供改进的电流限制。 差分电压放大器将输出电压与参考电压进行比较，并且控制通过晶体管以使输出电压基本上与参考电压相匹配。 这是通过感测电压调节器的输出电压来实现的，以将其应用于差分放大器的第一输入并将差分放大器的第二输入端耦合到参考电压。 电流检测晶体管利用电流镜像技术来检测通过传输晶体管的电流到输出。 将该感测电流与参考电流进行比较。 该比较的结果被反馈到差分电压放大器，以在感测电流超过参考电流的情况下增加明显感测的输出电压。

公开(公告)号：US20040155689A1

公开(公告)日：2004-08-12

申请号：US10739879

申请日：2003-12-18

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Manoj Kumar ,  Rajesh Narwal

IPC: H03K003/037

CPC classification number: H03K3/3565

Abstract: A differential input receiver with hysteresis on both sides of the reference voltage may include a two-input, one-output differential amplifier including two input transistors having a common terminal connected together. The control terminal of each transistor may be connected to one of the inputs of the differential amplifier. The output of the differential amplifier may be connected to a set of cascaded digital inverters/buffers, and an output of each digital buffer may be connected to the control terminal of a feedback transistor. The feedback transistor may be connected in parallel across each of the input transistors so that when one input voltage increases above or decreases below the input voltage at the second input by a predetermined threshold value, the feedback transistors operate to provide positive feedback to facilitate a rapid switching action at the output.

Abstract translation: 具有参考电压两侧的迟滞的差分输入接收器可以包括双输入单输出差分放大器，其包括连接在一起的共同端子的两个输入晶体管。 每个晶体管的控制端可以连接到差分放大器的一个输入端。 差分放大器的输出可以连接到一组级联的数字反相器/缓冲器，并且每个数字缓冲器的输出可以连接到反馈晶体管的控制端子。 反馈晶体管可以并联连接在每个输入晶体管上，使得当一个输入电压在第二输入处增加到或低于第二输入处的输入电压以下预定阈值时，反馈晶体管操作以提供正反馈以促进快速 在输出端切换动作。

公开(公告)号：US20040085230A1

公开(公告)日：2004-05-06

申请号：US10615601

申请日：2003-07-07

Applicant: STMicroelectronics Pvt. Ltd.

Inventor： Abhishek Lal

IPC: H03M007/00

CPC classification number: H03M7/16

Abstract: An improved binary decoder incorporating a selection circuit that activates a selected output corresponding to a input binary value, and a deselecting circuit coupled to each output that deactivates all other outputs when the selected output is activated. The deselecting circuit arrangement has a single input connected to the selected output and a plurality of outputs each of which is connected to one of the remaining outputs and forces them to the inactive state whenever the selected output is activated.

Abstract translation: 一种改进的二进制解码器，其包括激活对应于输入二进制值的所选输出的选择电路，以及耦合到每个输出的取消选择电路，当所选择的输出被激活时，其去激活所有其它输出。 取消选择电路装置具有连接到所选择的输出的单个输入和多个输出，每个输出连接到剩余输出中的一个，并且每当选择的输出被激活时迫使它们处于非活动状态。