-
21.发明申请公开(公告)号：US20250083951A1
公开(公告)日：2025-03-13
申请号：US18807103
申请日：2024-08-16
Applicant: STMicroelectronics International N.V.
Inventor： Andrea NOMELLINI , Ilaria GELMI , Federica CAPRA , Michele VIMERCATI , Luca LAMAGNA
Abstract: A process for manufacturing a microelectromechanical device includes: on a body containing semiconductor material, forming a sacrificial layer of dielectric material having a first surface, opposite to the body; conferring a sacrificial surface roughness to the first surface of the sacrificial layer; on the first surface of the sacrificial layer, forming a structural layer of semiconductor material having a second surface in contact with the first surface of the sacrificial layer. Conferring sacrificial surface roughness to the first surface of the sacrificial layer includes: on the sacrificial layer, forming a transfer layer of semiconductor material with intrinsic porosity; and partially removing the sacrificial layer through the transfer layer.
-
22.发明授权公开(公告)号：US12250804B2
公开(公告)日：2025-03-11
申请号：US18454471
申请日：2023-08-23
Applicant: STMicroelectronics International N.V.
Inventor： Shafquat Jahan Ahmed , Dhori Kedar Janardan
IPC: H10B10/00
Abstract: A memory cell including a set of active regions that overlay a set of gate regions to form a pair of cross-coupled inverters. A first active region extends along a first axis. A first gate region extends transversely to the first active region and overlays the first active region to form a first transistor of the pair of cross-coupled inverters. A second gate region extends transversely to the first active region and overlays the first active region to form a second transistor of the pair of cross-coupled inverters. A second active region extends along a second axis and overlays the first gate region to form a third transistor of the pair of cross-coupled inverters. A fourth active region extending along a third axis and overlays a gate region to form a transistor of a read port.
-
公开(公告)号：US20250078926A1
公开(公告)日：2025-03-06
申请号：US18817969
申请日：2024-08-28
Applicant: STMicroelectronics International N.V.
Inventor： Davide Manfré , Maurizio Francesco Perroni , Massimo Caruso , Fabio Enrico Carlo Disegni , Cesare Torti
IPC: G11C13/00
Abstract: A non-volatile memory includes a row decoder comprising, for each word-line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word-lines to ground. The row decoder comprises a demultiplexer connected to a second supply voltage smaller than the first, and configured to assert an enable signal as a function of an address signal. The switching circuit comprises two n-channel FETs connected in series between the word-line and ground, with the gate terminal of one FET connected to a first signal and the gate terminal of the other FET connected to a second voltage. A bias circuit is configured to set the voltage between the two FETs to the second voltage when the FETs are opened. The switching circuit comprises a p-channel FET connected between the word-line and the second voltage, and a gate terminal connected to a second signal.
-
公开(公告)号：US20250078883A1
公开(公告)日：2025-03-06
申请号：US18951392
申请日：2024-11-18
Applicant: STMicroelectronics International N.V.
Inventor： Harsh RAWAT , Kedar Janardan DHORI , Promod KUMAR , Nitin CHAWLA , Manuj AYODHYAWASI
Abstract: A memory array includes a plurality of bit-cells arranged as a set of rows of bit-cells intersecting a plurality of columns. The memory array also includes a plurality of in-memory-compute (IMC) cells arranged as a set of rows of IMC cells intersecting the plurality of columns of the memory array. Each of the IMC cells of the memory array includes a first bit-cell having a latch, a write-bit line and a complementary write-bit line, and a second bit-cell having a latch, a write-bit line and a complementary write-bit line, wherein the write-bit line of the first bit-cell is coupled to the complementary write-bit line of the second bit-cell and the complementary write-bit line of the first bit-cell is coupled to the write-bit line of the second bit-cell.
-
公开(公告)号：US20250076413A1
公开(公告)日：2025-03-06
申请号：US18459999
申请日：2023-09-01
Applicant: STMicroelectronics International N.V.
Inventor： Giulio RICOTTI , Alessandro SACCA' , Valeria BOTTAREL , Niccolo' BRAMBILLA
Abstract: Provided is a power converter including first, second, third and fourth nodes and a wire bonding test circuit. The wire bonding test circuit includes a multiplexer having a first terminal of a first side coupled to the first node and second and third terminals of a second side. The wire bonding test circuit includes a first switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the second node. The wire bonding test circuit includes a second switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the third node. The wire bonding test circuit includes a third switch having a first terminal coupled to the second terminal or the third terminal of the multiplexer and a second terminal coupled to the fourth node.
-
Patent Agency Ranking
26.发明申请公开(公告)号：US20250075370A1
公开(公告)日：2025-03-06
申请号：US18811164
申请日：2024-08-21
Applicant: STMicroelectronics International N.V.
Inventor： Björn MAGNUSSON LINDGREN , Mathias ISACSON
Abstract: A structure including a base portion (e.g., made of a graphite-based or graphene-based material) with at least one surface that is coated with a homogenous coating layer (e.g., made of silicon-carbide (SiC)). The homogenous coating layer prevents contaminants (e.g., carbon) from being released by the base portion into a cavity of a processing tool when heated to process one or more workpieces (e.g., silicon substrate, silicon wafers, etc.) present within the cavity. The homogenous coating layer includes grains and grain boundaries that are relatively the same size and shape as each other, which further prevents propagation of defects (e.g., cracking, peeling, etc.) that could potentially cause exposure of a region of the first surface of the base portion to the cavity of the processing tool contaminating the one or more workpieces present within the cavity of the processing tool.
-
27.发明授权公开(公告)号：US12243937B2
公开(公告)日：2025-03-04
申请号：US17711597
申请日：2022-04-01
Inventor： Matthieu Nongaillard , Thomas Oheix
IPC: H01L29/778 , H01L27/12 , H01L29/20 , H01L29/205 , H01L29/872
Abstract: The disclosure concerns a device which comprises a stack of two high electron mobility transistors, referred to as first and second transistor, separated by an insulating layer and each provided with a stack of semiconductor layers respectively referred to as first stack and second stack, the first and the second stack each comprising, from the insulating layer to, respectively, a first and a second surface, a barrier layer and a channel layer, the first and the second transistor respectively comprising a first set of electrodes and a second set of electrodes, the first and the second set of electrodes each comprising a source electrode, a drain electrode, and a gate electrode which are arranged so that the first and the second transistor are electrically connected head-to-tail.
-
公开(公告)号：US20250070785A1
公开(公告)日：2025-02-27
申请号：US18236038
申请日：2023-08-21
Applicant: STMicroelectronics International N.V.
Inventor： Venkata Narayanan SRINIVASAN , Ajay Kumar DIMRI
Abstract: A test-circuit includes a PLL-divider outputting first and third clock-signals as PLL clock-signals during functional mode and a capture-phase of transition and stuck-at-modes, and outputting a second clock-signal based upon an external clock-signal as an ATE clock-signal during a shift-phase of the transition and stuck-at-mode. An OCC passes the clock-signals in functional mode, transition capture mode, and stuck-at capture mode through sub-paths within first paths within first and second clock selection circuits so the first and third clock-signals are passed through less than the entire first paths, the sub-paths being first and second functional clock paths. In shift phase of transition and stuck-at-modes, the OCC passes the second clock-signal through sub-paths within second paths within the first and second clock selection circuits during the shift-phase so the second clock-signal is passed through less than the entire second paths, and through the first and second functional clock paths during the shift-phase.
-
公开(公告)号：US20250069652A1
公开(公告)日：2025-02-27
申请号：US18942973
申请日：2024-11-11
Applicant: STMicroelectronics International N.V.
Inventor： Kedar Janardan DHORI
IPC: G11C11/417 , G11C11/412
Abstract: Disclosed herein is a method of operating a static random access memory (SRAM) device in retention mode. The method includes powering an array of SRAM cells between first and second voltages in retention mode, detecting process variation information about the array of SRAM cells, and generating a control word based thereupon. The method continues with generating a reference voltage that is proportional to absolute temperature and having a magnitude curve that is set by the control word, and then maintaining the second voltage as being equal to the reference voltage.
-
公开(公告)号：US12237007B2
公开(公告)日：2025-02-25
申请号：US17852567
申请日：2022-06-29
Applicant: STMicroelectronics International N.V.
Inventor： Kedar Janardan Dhori , Harsh Rawat , Promod Kumar , Nitin Chawla , Manuj Ayodhyawasi
IPC: G11C11/418 , G11C11/412 , G11C11/419
Abstract: A circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit simultaneously actuates, through a word line driver circuit for each row, word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A bit line clamping circuit includes a sensing circuit that compares the analog voltages on a given pair of bit lines to a threshold voltage. A voltage clamp circuit is actuated in response to the comparison to preclude the analog voltages on the given pair of bit lines from decreasing below a clamping voltage level.
-
-
-
-
-
-
-
-
-
Search Results
1887
records
(took 0.032 seconds)
