公开(公告)号：US6110276A

公开(公告)日：2000-08-29

申请号：US28763

申请日：1998-02-24

Applicant: Jin Yu ,  Woong Sun Lee ,  Jung Keun Kim

Inventor： Jin Yu ,  Woong Sun Lee ,  Jung Keun Kim

IPC: H01L21/20 ,  C30B25/02 ,  H01L21/04 ,  C30B28/14 ,  C30B29/04 ,  H01L21/00 ,  H01L21/38

CPC classification number: H01L21/041 ,  C30B25/02 ,  C30B29/04 ,  H01L21/0405

Abstract: A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond film thus obtained is etched to peel off its surface. The n-type semiconducting diamond is superior in specific resistivity, 10.sup.-2 .OMEGA.cm or less.

Abstract translation: 通过使用其中n型杂质与金刚石沉积同时掺杂的CVD制备n型半导体金刚石的方法。 作为n型杂质，可以一次使用Li化合物和B化合物。 在掺杂之后，将如此获得的金刚石膜蚀刻以剥离其表面。 n型半导体金刚石的电阻率优于10-2欧米伽厘米或更小。

公开(公告)号：US08129627B2

公开(公告)日：2012-03-06

申请号：US12604586

申请日：2009-10-23

Applicant: Woong Sun Lee ,  Qwan Ho Chung ,  Ki Young Kim

Inventor： Woong Sun Lee ,  Qwan Ho Chung ,  Ki Young Kim

IPC: H05K1/16

CPC classification number: H05K1/185 ,  H01L23/293 ,  H01L23/5389 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/18162 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/1469

Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.

Abstract translation: 电路板包括具有上表面和连接到上表面的侧表面的半导体芯片。 接合焊盘设置在半导体芯片的上表面上。 凸块设置在焊盘上并从焊盘突出预定高度。 电路板主体具有凹部，并且半导体芯片位于凹部中，使得电路板主体在露出凸块的端部的同时覆盖半导体芯片的上表面和侧表面。 布线线设置在电路板主体上，并且布线的一部分位于凸块上方。 在凸起部分的一部分的一部分上形成开口以暴露凸起。 加强件物理和电连接暴露的凸块和布线。

公开(公告)号：US07880093B2

公开(公告)日：2011-02-01

申请号：US11693107

申请日：2007-03-29

Applicant: Woong Sun Lee

Inventor： Woong Sun Lee

IPC: H05K1/03

CPC classification number: H05K3/185 ,  H01L23/13 ,  H01L23/145 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/15157 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/183 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/182 ,  H05K2201/0215 ,  H05K2201/09845 ,  H05K2203/107 ,  Y10T428/12528 ,  H01L2924/00

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract translation: 用于实施多封装的基板包括下层，其具有包含导电填料的聚合物材料，并且设置有分为台阶部分和底部的阶梯状凹槽; 形成在下层之上的涂层，形成涂层，使得其可以在台阶部分上形成金属线形成区域，并且在金属线形成区域中的阶梯状沟槽和导电填料的底部 被暴露 以及金属线，其通过使用在由涂层限定的金属线形成区域中的暴露的导电填料作为种子层的电镀工艺形成。

公开(公告)号：US20090321892A1

公开(公告)日：2009-12-31

申请号：US12192173

申请日：2008-08-15

Applicant: Han Jun BAE ,  Woong Sun LEE

Inventor： Han Jun BAE ,  Woong Sun LEE

IPC: H01L23/488

CPC classification number: H01L23/53276 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract translation: 半导体封装包括具有多个焊盘的半导体芯片。 在半导体芯片中形成贯通电极，与导体焊盘电连接。 贯通电极包括由导体限定的多个导体和多个空隙。 每个导体可以包括分组成具有多个空隙的球形的多个纳米线，多个纳米线分组成具有多个空隙的多边形，或者导体可以包括多个微焊球。 通过电极的空隙吸收在半导体封装的驱动期间产生磁头时引起的应力。

公开(公告)号：US07387910B2

公开(公告)日：2008-06-17

申请号：US11403538

申请日：2006-04-13

Applicant: Woong-Sun Lee ,  Jin Yu

Inventor： Woong-Sun Lee ,  Jin Yu

IPC: H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L23/52 ,  H01L23/48 ,  H01L23/40

CPC classification number: H01L24/13 ,  H01L24/02 ,  H01L24/06 ,  H01L24/11 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/13099 ,  H01L2224/132 ,  H01L2224/13287 ,  H01L2224/1329 ,  H01L2224/136 ,  H01L2224/1403 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00 ,  H01L2924/0001 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H05K3/3436 ,  H05K3/3484 ,  H05K2201/0212 ,  H05K2201/094 ,  H05K2201/10234 ,  H05K2201/10674 ,  H05K2203/041 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/00014

Abstract: Disclosed herein is a method of bonding solder pads of a flip-chip package. This invention relates to a method of bonding solder pads having different sizes to each other, when a bonding operation is executed between a chip and a PCB, between chips, or between PCBs. On a side having a larger solder pad, a general solder ball is used. Conversely, on a side having a smaller solder pad, a solder ball having a core is used. The core serves to maintain a predetermined interval between the chip and the PCB or between the chips, after the bonding operation has been completed. The solder bonded parts are aligned with each other so as to perform a final bonding operation. In a conventional flip-chip package, solder pads provided on a bonded part must have the same or similar size. According to this invention, even if the size difference between the solder pads is large, bonding is possible, thus ensuring electrical and mechanical reliability.

Abstract translation: 这里公开了一种焊接倒装芯片封装的焊盘的方法。 本发明涉及当在芯片和PCB之间，芯片之间或PCB之间执行接合操作时，将彼此不同尺寸的焊盘焊接的方法。 在具有较大焊盘的一侧，使用一般的焊球。 相反，在具有较小焊盘的一侧使用具有芯的焊球。 芯片用于在焊接操作完成之后保持芯片和PCB之间或芯片之间的预定间隔。 焊接接合部彼此对准，以进行最终接合操作。 在传统的倒装芯片封装中，设置在接合部件上的焊盘必须具有相同或相似的尺寸。 根据本发明，即使焊盘之间的尺寸差大，也可以进行接合，从而确保电气和机械的可靠性。

公开(公告)号：US20080081209A1

公开(公告)日：2008-04-03

申请号：US11693107

申请日：2007-03-29

Applicant: Woong Sun Lee

Inventor： Woong Sun Lee

IPC: H01L29/12 ,  H01L21/3205

CPC classification number: H05K3/185 ,  H01L23/13 ,  H01L23/145 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/15157 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/183 ,  H05K3/0026 ,  H05K3/0032 ,  H05K3/182 ,  H05K2201/0215 ,  H05K2201/09845 ,  H05K2203/107 ,  Y10T428/12528 ,  H01L2924/00

Abstract: A substrate for embodying multi-package comprises an underlying layer has a polymer material containing a conductive filler and provided with a step-like groove divided into step part and bottom part; a coating layer formed over the underlying layer, the coating layer is formed so that it may define a metal-wire forming area on the step part and the bottom part of the step-like groove and the conductive filler in the metal-wire forming area is exposed; and a metal wire formed via a plating process using the exposed conductive filler in the metal-wire forming area defined by the coating layer as a seed layer.

Abstract translation: 用于实施多封装的基板包括下层，其具有包含导电填料的聚合物材料，并且设置有分为台阶部分和底部的阶梯状凹槽; 形成在下层之上的涂层，形成涂层，使得其可以在台阶部分上形成金属线形成区域，并且在金属线形成区域中的阶梯状沟槽和导电填料的底部 被暴露 以及金属线，其通过使用在由涂层限定的金属线形成区域中的暴露的导电填料作为种子层的电镀工艺形成。