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    Method of fabricating semiconductor package
    2.
    发明授权
    Method of fabricating semiconductor package 有权
    制造半导体封装的方法

    公开(公告)号：US08445322B2

    公开(公告)日：2013-05-21

    申请号：US13241472

    申请日：2011-09-23

    Applicant: Woong Sun Lee ,  Qwan Ho Chung

    Inventor： Woong Sun Lee ,  Qwan Ho Chung

    IPC: H01L21/00 ,  H01L23/02

    CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

    Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。

    Stack type semiconductor package
    3.
    发明授权
    Stack type semiconductor package 有权
    堆叠型半导体封装

    公开(公告)号：US08796834B2

    公开(公告)日：2014-08-05

    申请号：US13118714

    申请日：2011-05-31

    Applicant: Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

    Inventor： Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

    IPC: H01L23/522

    CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/82 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

    Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.

    Abstract translation: 堆叠包括具有第一表面和第二表面的芯层，并且包括第一电路布线; 设置在所述芯层的第二表面上的第一半导体器件; 形成在所述芯层的第二表面上以覆盖所述第一半导体器件的第一树脂层; 形成在第一树脂层上并与第一半导体器件电连接的第二电路布线; 设置在包括第二电路布线的第一树脂层上并与第二电路布线电连接的第二半导体装置; 第二树脂层，形成在第二电路布线和第一树脂层上以覆盖第二半导体器件; 以及形成为穿过第一树脂层和芯层并且电连接第一电路布线和第二电路布线的多个通孔图案。

    Stacked semiconductor package and method for fabricating the same
    5.
    发明授权
    Stacked semiconductor package and method for fabricating the same 有权
    叠层半导体封装及其制造方法

    公开(公告)号：US08053879B2

    公开(公告)日：2011-11-08

    申请号：US12261223

    申请日：2008-10-30

    Applicant: Woong Sun Lee ,  Qwan Ho Chung

    Inventor： Woong Sun Lee ,  Qwan Ho Chung

    IPC: H01L23/02

    CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

    Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。

    Semiconductor package having chip selection through electrodes and stacked semiconductor package having the same
    7.
    发明授权
    Semiconductor package having chip selection through electrodes and stacked semiconductor package having the same 有权
    具有通过电极进行芯片选择的半导体封装和具有该半导体封装的堆叠半导体封装

    公开(公告)号：US08030739B2

    公开(公告)日：2011-10-04

    申请号：US12260172

    申请日：2008-10-29

    Applicant: Qwan Ho Chung

    Inventor： Qwan Ho Chung

    IPC: H01L29/40 ,  H01L21/44

    CPC classification number: G11C5/02 ,  H01L23/481 ,  H01L25/0657 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A stacked semiconductor package includes a plurality of stacked semiconductor chips each having a circuit unit, a data pad, and a chip selection pad. The plurality of stacked semiconductor chips also includes a plurality of chip selection through electrodes. The chip selection through electrodes penetrate the chip selection pads and the semiconductor chips, and the chip selection through electrodes receive chip selection signals. The chip selection pad of a semiconductor chip is electrically connected to the chip selection through electrode that receives the chip selection signal for selecting the semiconductor chip. The chip selection pad is electrically insulated from the chip selection through electrodes for receiving the chip selection signal for selecting a different semiconductor chip.

    Abstract translation: 堆叠的半导体封装包括多个堆叠的半导体芯片，每个堆叠的半导体芯片具有电路单元，数据焊盘和芯片选择板。 多个层叠半导体芯片还包括多个芯片选择贯通电极。 通过电极的芯片选择穿透芯片选择焊盘和半导体芯片，并且通过电极的芯片选择接收芯片选择信号。 半导体芯片的芯片选择焊盘与接收用于选择半导体芯片的芯片选择信号的芯片选择贯通电极电连接。 芯片选择焊盘与芯片选择通过电极电绝缘，用于接收用于选择不同半导体芯片的芯片选择信号。

    Wafer level package configured to compensate size difference in different types of packages
    9.
    发明授权
    Wafer level package configured to compensate size difference in different types of packages 失效
    晶圆级封装配置为补偿不同类型封装的尺寸差异

    公开(公告)号：US07629682B2

    公开(公告)日：2009-12-08

    申请号：US11647622

    申请日：2006-12-29

    Applicant: Seung Taek Yang ,  Qwan Ho Chung

    Inventor： Seung Taek Yang ,  Qwan Ho Chung

    IPC: H01L23/12 ,  H01L21/00

    CPC classification number: H01L23/525 ,  H01L23/3114 ,  H01L23/367 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A wafer level package including a semiconductor chip having a plurality of bonding pads on a front surface thereof; a lower insulation layer formed on the semiconductor chip to expose the bonding pads; re-distribution lines formed on the lower insulation layer to be connected to the bonding pads at first ends thereof; an upper insulation layer formed on the lower insulation layer including the re-distribution lines, with portions of the re-distribution lines exposed; solder balls attached to the exposed portions of the re-distribution lines; and a cap covering a rear surface of the semiconductor chip.

    Abstract translation: 一种晶片级封装，包括在其前表面上具有多个焊盘的半导体芯片; 形成在所述半导体芯片上以暴露所述接合焊盘的下绝缘层; 形成在下绝缘层上的再分配线在其第一端连接到接合焊盘; 形成在包括再分配线的下绝缘层上的上绝缘层，再分配线的一部分暴露; 附着在再分配线路的暴露部分的焊球; 以及覆盖半导体芯片的后表面的盖。

    Semiconductor chip package and method for fabricating the same
    10.
    发明授权
    Semiconductor chip package and method for fabricating the same 有权
    半导体芯片封装及其制造方法

    公开(公告)号：US07445961B2

    公开(公告)日：2008-11-04

    申请号：US12030324

    申请日：2008-02-13

    Applicant: Qwan Ho Chung

    Inventor： Qwan Ho Chung

    IPC: H01L21/00

    CPC classification number: H01L23/564 ,  H01L21/563 ,  H01L23/3192 ,  H01L23/5256 ,  H01L24/29 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/83194 ,  H01L2224/8385 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00

    Abstract: Disclosed are a semiconductor chip package and a method for fabricating the same. The semiconductor chip package includes a semiconductor chip and a circuit board. The semiconductor chip is bonded to the circuit board by means of adhesive except for a metal-exposed region of the semiconductor chip. Anti-migration material is formed between the circuit board and a predetermined portion of the semiconductor chip, in which the predetermined portion of the semiconductor chip has no adhesive, in order to prevent material contained in the metal trace from migrating to the metal-exposed region of the semiconductor chip. A lamination phenomenon is not created between the circuit board and the semiconductor chip after the HAST has been carried out.

    Abstract translation: 公开了一种半导体芯片封装及其制造方法。 半导体芯片封装包括半导体芯片和电路板。 除了半导体芯片的金属曝光区域之外，通过粘合剂将半导体芯片接合到电路板。 防电迁移材料形成在电路板和半导体芯片的预定部分之间，其中半导体芯片的预定部分没有粘合剂，以防止包含在金属迹线中的材料迁移到金属暴露区域 的半导体芯片。 在执行HAST之后，在电路板和半导体芯片之间不产生叠层现象。

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