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    Method for making n-type semiconductor diamond
    1.
    发明授权
    Method for making n-type semiconductor diamond 失效
    制造n型半导体金刚石的方法

    公开(公告)号：US6110276A

    公开(公告)日：2000-08-29

    申请号：US28763

    申请日：1998-02-24

    Applicant: Jin Yu ,  Woong Sun Lee ,  Jung Keun Kim

    Inventor： Jin Yu ,  Woong Sun Lee ,  Jung Keun Kim

    IPC: H01L21/20 ,  C30B25/02 ,  H01L21/04 ,  C30B28/14 ,  C30B29/04 ,  H01L21/00 ,  H01L21/38

    CPC classification number: H01L21/041 ,  C30B25/02 ,  C30B29/04 ,  H01L21/0405

    Abstract: A method for making n-type semiconducting diamond by use of CVD in which n-type impurities are doped simultaneously with the deposition of diamond. As the n-type impurities, an Li compound and a B compound, both, are used at once. After doping, a diamond film thus obtained is etched to peel off its surface. The n-type semiconducting diamond is superior in specific resistivity, 10.sup.-2 .OMEGA.cm or less.

    Abstract translation: 通过使用其中n型杂质与金刚石沉积同时掺杂的CVD制备n型半导体金刚石的方法。 作为n型杂质，可以一次使用Li化合物和B化合物。 在掺杂之后，将如此获得的金刚石膜蚀刻以剥离其表面。 n型半导体金刚石的电阻率优于10-2欧米伽厘米或更小。

    Semiconductor package using through-electrodes having voids
    2.
    发明授权
    Semiconductor package using through-electrodes having voids 失效
    使用具有空隙的通孔的半导体封装

    公开(公告)号：US08618637B2

    公开(公告)日：2013-12-31

    申请号：US12192173

    申请日：2008-08-15

    Applicant: Han Jun Bae ,  Woong Sun Lee

    Inventor： Han Jun Bae ,  Woong Sun Lee

    IPC: H01L23/488

    CPC classification number: H01L23/53276 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

    Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

    Abstract translation: 半导体封装包括具有多个焊盘的半导体芯片。 在半导体芯片中形成贯通电极，与导体焊盘电连接。 贯通电极包括由导体限定的多个导体和多个空隙。 每个导体可以包括分组成具有多个空隙的球形的多个纳米线，多个纳米线分组成具有多个空隙的多边形，或者导体可以包括多个微焊球。 通过电极的空隙吸收在半导体封装的驱动期间产生磁头时引起的应力。

    Method of fabricating semiconductor package
    5.
    发明授权
    Method of fabricating semiconductor package 有权
    制造半导体封装的方法

    公开(公告)号：US08445322B2

    公开(公告)日：2013-05-21

    申请号：US13241472

    申请日：2011-09-23

    Applicant: Woong Sun Lee ,  Qwan Ho Chung

    Inventor： Woong Sun Lee ,  Qwan Ho Chung

    IPC: H01L21/00 ,  H01L23/02

    CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

    Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。

    Stack type semiconductor package
    7.
    发明授权
    Stack type semiconductor package 有权
    堆叠型半导体封装

    公开(公告)号：US08796834B2

    公开(公告)日：2014-08-05

    申请号：US13118714

    申请日：2011-05-31

    Applicant: Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

    Inventor： Jin Ho Bae ,  Qwan Ho Chung ,  Woong Sun Lee

    IPC: H01L23/522

    CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/82 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2924/00013 ,  H01L2924/01029 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00

    Abstract: A stack package includes a core layer having a first surface and a second surface, and including first circuit wiring lines; a first semiconductor device disposed on the second surface of the core layer; a first resin layer formed on the second surface of the core layer to cover the first semiconductor device; second circuit wiring lines formed on the first resin layer and electrically connected with the first semiconductor device; a second semiconductor device disposed over the first resin layer including the second circuit wiring lines and electrically connected with the second circuit wiring lines; a second resin layer formed on the second circuit wiring lines and the first resin layer to cover the second semiconductor device; and a plurality of via patterns formed to pass through the first resin layer and the core layer and electrically connecting the first circuit wiring lines and the second circuit wiring lines.

    Abstract translation: 堆叠包括具有第一表面和第二表面的芯层，并且包括第一电路布线; 设置在所述芯层的第二表面上的第一半导体器件; 形成在所述芯层的第二表面上以覆盖所述第一半导体器件的第一树脂层; 形成在第一树脂层上并与第一半导体器件电连接的第二电路布线; 设置在包括第二电路布线的第一树脂层上并与第二电路布线电连接的第二半导体装置; 第二树脂层，形成在第二电路布线和第一树脂层上以覆盖第二半导体器件; 以及形成为穿过第一树脂层和芯层并且电连接第一电路布线和第二电路布线的多个通孔图案。

    Stacked semiconductor package and method for fabricating the same
    9.
    发明授权
    Stacked semiconductor package and method for fabricating the same 有权
    叠层半导体封装及其制造方法

    公开(公告)号：US08053879B2

    公开(公告)日：2011-11-08

    申请号：US12261223

    申请日：2008-10-30

    Applicant: Woong Sun Lee ,  Qwan Ho Chung

    Inventor： Woong Sun Lee ,  Qwan Ho Chung

    IPC: H01L23/02

    CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

    Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

    Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。

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