公开(公告)号：US08618637B2

公开(公告)日：2013-12-31

申请号：US12192173

申请日：2008-08-15

Applicant: Han Jun Bae ,  Woong Sun Lee

Inventor： Han Jun Bae ,  Woong Sun Lee

IPC: H01L23/488

CPC classification number: H01L23/53276 ,  H01L23/3128 ,  H01L23/481 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/15311

Abstract: A semiconductor package includes a semiconductor chip having a plurality of bonding pads. Through-electrodes are formed in the semiconductor chip and are electrically connected to the bonding pads. The through electrodes comprise a plurality of conductors and a plurality of voids that are defined by the conductors. Each conductor may include a plurality of nanowires grouped into a spherical shape having a plurality of voids, a plurality of nanowires grouped into a polygonal shape having a plurality of voids, or the conductors may include a plurality of micro solder balls. The voids of the through electrode absorb stress caused when head is generated during the driving of the semiconductor package.

Abstract translation: 半导体封装包括具有多个焊盘的半导体芯片。 在半导体芯片中形成贯通电极，与导体焊盘电连接。 贯通电极包括由导体限定的多个导体和多个空隙。 每个导体可以包括分组成具有多个空隙的球形的多个纳米线，多个纳米线分组成具有多个空隙的多边形，或者导体可以包括多个微焊球。 通过电极的空隙吸收在半导体封装的驱动期间产生磁头时引起的应力。

公开(公告)号：US08399998B2

公开(公告)日：2013-03-19

申请号：US12604601

申请日：2009-10-23

Applicant: Ki Young Kim ,  Sung Ho Hyun ,  Myung Geun Park ,  Woong Sun Lee

Inventor： Ki Young Kim ,  Sung Ho Hyun ,  Myung Geun Park ,  Woong Sun Lee

IPC: H01L23/48

CPC classification number: H01L23/3114 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/24145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/4847 ,  H01L2224/4911 ,  H01L2224/49176 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/92 ,  H01L2225/0651 ,  H01L2225/06524 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06551 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15165 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/85 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A semiconductor package includes a semiconductor chip having a first surface, a second surface located opposite the first surface, and side surfaces connecting the first and second surfaces. The semiconductor chip includes bonding pads disposed on the first surface and having a molding member formed to cover the first surface of the semiconductor chip. The molding member is formed so as to expose the side surfaces of the semiconductor chip. The semiconductor chip also includes bonding members having first ends electrically connected to the respective bonding pads and second ends that are connected to and opposite the first ends. The second ends are exposed from side surfaces of the molding member after passing through the molding member so as to allow various electrical connections.

Abstract translation: 半导体封装包括具有第一表面，与第一表面相对的第二表面和连接第一表面和第二表面的侧表面的半导体芯片。 半导体芯片包括设置在第一表面上并具有形成为覆盖半导体芯片的第一表面的成型构件的接合焊盘。 模制构件形成为暴露半导体芯片的侧表面。 半导体芯片还包括具有电连接到各个焊盘的第一端和连接到第一端并与其相对的第二端的接合构件。 第二端在通过模制构件之后从模制构件的侧表面暴露以允许各种电连接。

公开(公告)号：US20120205798A1

公开(公告)日：2012-08-16

申请号：US13365473

申请日：2012-02-03

Applicant: Si Han KIM ,  Woong Sun LEE

Inventor： Si Han KIM ,  Woong Sun LEE

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/82 ,  H01L23/3128 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311

Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.

Abstract translation: 半导体封装包括具有突出地形成在其上的第一凸块的第一半导体芯片; 覆盖在第一半导体芯片上以嵌入第一半导体芯片的第一铜箔附着树脂，并且形成为使得附着在第一铜箔附着树脂的上表面上的第一铜箔层与第一凸块电连接; 第二铜箔附着树脂，包括与第一铜箔层电连接的第二铜箔层，并且设置在第一铜箔附着树脂上; 以及以与面对第一半导体芯片的方式嵌入第二铜箔附着树脂中的第二半导体芯片，并且形成有与第二铜箔层电连接的第二凸块。

公开(公告)号：US20120015477A1

公开(公告)日：2012-01-19

申请号：US13241472

申请日：2011-09-23

Applicant: Woong Sun LEE ,  Qwan Ho CHUNG

Inventor： Woong Sun LEE ,  Qwan Ho CHUNG

IPC: H01L21/60

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。

公开(公告)号：US20100326715A1

公开(公告)日：2010-12-30

申请号：US12604586

申请日：2009-10-23

Applicant: Woong Sun LEE ,  Qwan Ho CHUNG ,  Ki Young KIM

Inventor： Woong Sun LEE ,  Qwan Ho CHUNG ,  Ki Young KIM

IPC: H05K1/18

CPC classification number: H05K1/185 ,  H01L23/293 ,  H01L23/5389 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06155 ,  H01L2224/06156 ,  H01L2224/12105 ,  H01L2224/2101 ,  H01L2224/2105 ,  H01L2224/211 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/18162 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K2201/0969 ,  H05K2201/10674 ,  H05K2203/1469

Abstract: A circuit board includes a semiconductor chip having an upper surface and side surfaces connected to the upper surface. A bonding pad is disposed on the upper surface of the semiconductor chip. A bump is disposed on the bonding pad and projects from the bonding pad by a predetermined height. A circuit board body has a recess part, and the semiconductor chip is positioned in the recess part so that the circuit board body covers the upper surface and the side surfaces of the semiconductor chip while exposing an end of the bump. A wiring line is disposed on the circuit board body and part of the wiring line is positioned over the bump. An opening is formed in a portion of the part of the wiring line over the bump to expose the bump. A reinforcing member physically and electrically connects the exposed bump and the wiring line.

Abstract translation: 电路板包括具有上表面和连接到上表面的侧表面的半导体芯片。 接合焊盘设置在半导体芯片的上表面上。 凸块设置在焊盘上并从焊盘突出预定高度。 电路板主体具有凹部，并且半导体芯片位于凹部中，使得电路板主体在露出凸块的端部的同时覆盖半导体芯片的上表面和侧表面。 布线线设置在电路板主体上，并且布线的一部分位于凸块上方。 在凸起部分的一部分的一部分上形成开口以暴露凸起。 加强件物理和电连接暴露的凸块和布线。

公开(公告)号：US20100142118A1

公开(公告)日：2010-06-10

申请号：US12492835

申请日：2009-06-26

Applicant: Woong Sun LEE

Inventor： Woong Sun LEE

IPC: H05K1/18 ,  H01G4/224

CPC classification number: H05K1/162 ,  H01G4/12 ,  H01G4/33 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/642 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/4824 ,  H01L2224/484 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01021 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H05K1/0373 ,  H05K2201/0209 ,  H05K2201/09309 ,  H05K2201/2036 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A copper-clad laminate with a capacitor, a printed circuit board having the same and a semiconductor package having the printed circuit board are presented. The copper-clad laminate with the capacitor includes a first and second conductive layers, a film body, and thickness uniformity improving members. The first and second conductive layers are aligned to be substantially in parallel to each other and thus oppose each other. The film body is interposed between the first and the second conductive layer. The thickness uniformity improving members are also interposed between the first and second conductive layers and are inserted within the film body. The thickness uniformity improving members have one end connected to the first conductive layer and have the opposing ends connected to the second conductive layer.

Abstract translation: 本发明提供一种具有电容器的覆铜层压板，具有该电路板的印刷电路板和具有印刷电路板的半导体封装。 具有电容器的覆铜层压板包括第一和第二导电层，膜体和厚度均匀性改善构件。 第一和第二导电层被对齐以彼此基本上平行并因此彼此相对。 胶片体介于第一和第二导电层之间。 厚度均匀性改善构件也插入在第一和第二导电层之间并插入到膜体内。 厚度均匀性改善构件的一端连接到第一导电层并且具有连接到第二导电层的相对端。

公开(公告)号：US20090174073A1

公开(公告)日：2009-07-09

申请号：US12254884

申请日：2008-10-21

Applicant: Woong Sun LEE

Inventor： Woong Sun LEE

IPC: H01L23/52 ,  H01L21/00

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2924/0002 ,  H05K3/06 ,  H05K3/247 ,  H05K3/3457 ,  H05K2201/035 ,  H05K2201/09436 ,  H01L2924/00

Abstract: A substrate for a semiconductor package includes a ball land disposed on one surface of an insulating layer. A solder resist is applied to the surface of insulating layer while leaving the ball land exposed. A coating film is applied on the exposed surface of the 1o ball land. The coating film includes a high molecular compound having metal particles. In the substrate having the ball land with the coating film formed thereon, it is not necessary to subject the substrate to a UBM formation process.

Abstract translation: 用于半导体封装的衬底包括设置在绝缘层的一个表面上的球形区域。 在绝缘层的表面上施加阻焊剂，同时露出球场。 将涂膜施加在1o球地的暴露表面上。 涂膜包括具有金属颗粒的高分子化合物。 在其上形成有涂膜的球面的基板中，不需要使基板进行UBM形成工艺。

公开(公告)号：US20090140426A1

公开(公告)日：2009-06-04

申请号：US11965365

申请日：2007-12-27

Applicant: Woong Sun LEE ,  Il Hwan CHO ,  Myung Geun PARK ,  Cheol Ho JOH ,  Eun Hye DO ,  Ki Young KIM ,  Ji Eun KIM ,  Jong Hyun NAM

Inventor： Woong Sun LEE ,  Il Hwan CHO ,  Myung Geun PARK ,  Cheol Ho JOH ,  Eun Hye DO ,  Ki Young KIM ,  Ji Eun KIM ,  Jong Hyun NAM

IPC: H01L23/48 ,  H01L21/02

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81191 ,  H01L2224/81205 ,  H01L2224/81395 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12044 ,  H05K3/282 ,  H05K2201/10674 ,  H05K2203/0568 ,  H05K2203/1361 ,  H05K2203/1554 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A flip chip package includes a substrate and a semiconductor chip. The substrate includes a substrate body, a metal wiring having a terminal part some of which is disposed in the substrate body, a solder resist pattern formed on the substrate body with an opening for exposing the terminal part, and an organic anti-oxidation layer for covering the terminal part. The semiconductor chip has a bump formed through (e.g., penetrates) the organic anti-oxidation layer and is electrically connected to the terminal part. The present invention prevents oxidation of the terminal part and allows easy coupling of a bump of a semiconductor chip and the terminal part of the substrate, since an anti-oxidation layer including an organic matter is formed over a surface of a terminal part including copper which is easily oxidized.

Abstract translation: 倒装芯片封装包括衬底和半导体芯片。 基板包括基板主体，具有端子部分的金属布线，其中一部分设置在基板主体中，形成在基板主体上的阻焊图案具有用于暴露端子部分的开口，以及有机抗氧化层， 覆盖终端部分。 半导体芯片具有穿过（例如，穿透）有机抗氧化层并且电连接到端子部分的凸块。 本发明防止了端子部分的氧化，并且容易地将半导体芯片的凸起与基板的端子部分耦合，因为包括有机物的抗氧化层在包括铜的端子部分的表面上形成 容易氧化。

公开(公告)号：US08558380B2

公开(公告)日：2013-10-15

申请号：US13365473

申请日：2012-02-03

Applicant: Si Han Kim ,  Woong Sun Lee

Inventor： Si Han Kim ,  Woong Sun Lee

IPC: H01L23/498 ,  H01L21/56

CPC classification number: H01L24/82 ,  H01L23/3128 ,  H01L24/24 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/82105 ,  H01L2224/92244 ,  H01L2225/1023 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/15311

Abstract: A semiconductor package includes a first semiconductor chip having first bumps which are projectedly formed thereon; a first copper foil attachment resin covered on the first semiconductor chip to embed the first semiconductor chip, and formed such that a first copper foil layer attached on an upper surface of the first copper foil attachment resin is electrically connected with the first bumps; a second copper foil attachment resin including a second copper foil layer which is electrically connected with the first copper foil layer, and disposed on the first copper foil attachment resin; and a second semiconductor chip embedded in the second copper foil attachment resin in such a way as to face the first semiconductor chip, and having second bumps formed thereon which are electrically connected with the second copper foil layer.

Abstract translation: 半导体封装包括具有突出地形成在其上的第一凸块的第一半导体芯片; 覆盖在第一半导体芯片上以嵌入第一半导体芯片的第一铜箔附着树脂，并且形成为使得附着在第一铜箔附着树脂的上表面上的第一铜箔层与第一凸块电连接; 第二铜箔附着树脂，包括与第一铜箔层电连接的第二铜箔层，并且设置在第一铜箔附着树脂上; 以及以与面对第一半导体芯片的方式嵌入第二铜箔附着树脂中的第二半导体芯片，并且形成有与第二铜箔层电连接的第二凸块。

公开(公告)号：US08445322B2

公开(公告)日：2013-05-21

申请号：US13241472

申请日：2011-09-23

Applicant: Woong Sun Lee ,  Qwan Ho Chung

Inventor： Woong Sun Lee ,  Qwan Ho Chung

IPC: H01L21/00 ,  H01L23/02

CPC classification number: H01L22/14 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H01L2224/0401

Abstract: A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

Abstract translation: 本发明提供一种具有单元封装，盖基板，粘合件和连接电极的叠层半导体封装。 单元封装包括衬底，第一电路图案和第二电路图案。 第一电路图案设置在基板的上表面上。 第二电路图案设置在衬底的下表面上。 基板的下表面和上表面彼此相对。 第一和第二半导体芯片分别电连接到第一和第二电路图案。 盖基板与第一半导体芯片和第二半导体芯片相对。 粘合剂部件分别介于单元封装和盖基板之间。 连接电极通过单元封装，盖基板和粘合构件，并且电连接到第一和第二电路图案。