公开(公告)号：US08884861B2

公开(公告)日：2014-11-11

申请号：US12421618

申请日：2009-04-09

Applicant: Young-Wook Lee ,  Hwa-Yeul Oh ,  Pil-Sang Yun ,  Je-Hyeong Park

Inventor： Young-Wook Lee ,  Hwa-Yeul Oh ,  Pil-Sang Yun ,  Je-Hyeong Park

IPC: G02F1/1362 ,  G09G3/36 ,  G02F1/1343

CPC classification number: G02F1/13306 ,  G02F1/136213 ,  G02F1/13624 ,  G02F2001/134345 ,  G09G3/3659 ,  G09G2300/0443 ,  G09G2300/0447 ,  G09G2300/0809 ,  G09G2300/0876 ,  G09G2320/028

Abstract: Embodiments of the present invention relate to a liquid crystal display and a driving method thereof. According to an embodiment, the liquid crystal display comprises a pixel electrode having a first subpixel electrode, a second subpixel electrode, and a third subpixel electrode electrically separated from each other. The liquid crystal display comprises a first thin film transistor connected to the first subpixel electrode, a second thin film transistor connected to the second subpixel electrode, a third thin film transistor connected to the third subpixel electrode, and a fourth thin film transistor connected to the second subpixel electrode and the third subpixel electrode. The liquid crystal display comprises a first gate line connected to the first to third thin film transistors, a second gate line connected to the fourth thin film transistor, a data line connected to the first and second thin film transistors, and a storage electrode line connected to the third thin film transistor.

Abstract translation: 本发明的实施例涉及一种液晶显示器及其驱动方法。 根据实施例，液晶显示器包括具有彼此电分离的第一子像素电极，第二子像素电极和第三子像素电极的像素电极。 液晶显示器包括连接到第一子像素电极的第一薄膜晶体管，连接到第二子像素电极的第二薄膜晶体管，连接到第三子像素电极的第三薄膜晶体管和连接到第三子像素电极的第四薄膜晶体管 第二子像素电极和第三子像素电极。 液晶显示器包括连接到第一至第三薄膜晶体管的第一栅极线，连接到第四薄膜晶体管的第二栅极线，连接到第一和第二薄膜晶体管的数据线，以及连接到第一和第二薄膜晶体管的存储电极线 到第三薄膜晶体管。

公开(公告)号：US08853699B2

公开(公告)日：2014-10-07

申请号：US12902786

申请日：2010-10-12

Applicant: Seung-Ha Choi ,  Kyoung-Jae Chung ,  Young-Wook Lee

Inventor： Seung-Ha Choi ,  Kyoung-Jae Chung ,  Young-Wook Lee

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/66969

Abstract: Disclosed are a thin film transistor and a method of forming the thin film transistor, wherein the thin film transistor includes a gate electrode, an oxide semiconductor pattern, a first gate insulating layer pattern interposed between the gate electrode and the oxide semiconductor pattern, wherein the first gate insulating layer pattern has an island shape or has two portions of different thicknesses from each other, a source electrode and a drain electrode electrically connected to the oxide semiconductor pattern, wherein the source electrode and the drain electrode are separated from each other, and a first insulating layer pattern placed between the source electrode and drain electrode and the oxide semiconductor pattern, wherein the first insulating layer pattern partially contacts the source electrode and drain electrode and the first gate insulating layer pattern, and wherein the first insulating layer is enclosed by an outer portion.

Abstract translation: 公开了一种薄膜晶体管和形成薄膜晶体管的方法，其中薄膜晶体管包括栅电极，氧化物半导体图案，插入在栅电极和氧化物半导体图案之间的第一栅绝缘层图案，其中 第一栅极绝缘层图案具有岛状或具有彼此不同厚度的两个部分，与氧化物半导体图案电连接的源电极和漏电极，其中源电极和漏电极彼此分离，以及 位于源电极和漏极之间的第一绝缘层图案和氧化物半导体图案，其中第一绝缘层图案部分地接触源电极和漏电极以及第一栅极绝缘层图案，并且其中第一绝缘层被 外部。

公开(公告)号：US08730420B2

公开(公告)日：2014-05-20

申请号：US13419228

申请日：2012-03-13

Applicant: Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC: G02F1/136 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/136209 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.

Abstract translation: 提供了一种液晶显示器，用于防止光泄漏，同时提高了开口率和减少了数据线的负载。 液晶显示器包括形成在绝缘基板上并且彼此分开的栅极线和存储电极线，与栅极线相交的第一数据线和第二数据线，由栅极线和第一栅极线限定的第一像素电极 数据线和由栅极线和第二数据线限定并与第一像素电极相邻的第二像素电极。 此外，包括第一像素电极和第二像素电极之间的阻挡电极，其中第一数据线的至少一部分设置在第一像素电极下方，并且阻挡电极的至少一部分设置在第二像素电极下方 并且除了第一条数据线之外。

公开(公告)号：US08604469B2

公开(公告)日：2013-12-10

申请号：US12464920

申请日：2009-05-13

Applicant: Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Young-Wook Lee ,  Jong-In Kim

Inventor： Woo-Geun Lee ,  Jae-Hyoung Youn ,  Ki-Won Kim ,  Young-Wook Lee ,  Jong-In Kim

IPC: H01L29/10

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L29/78696

Abstract: A thin film transistor array panel includes a substrate, a gate line formed on the substrate and including a gate electrode, a gate insulating layer formed on the gate line, a semiconductor formed on the gate insulating layer and including a channel of a thin film transistor, a data line formed on the semiconductor and including a source electrode and a drain electrode formed on the semiconductor and opposite to the source electrode with respect to the channel of the thin film transistor, wherein the channel of the thin film transistor covers both side surfaces of the gate electrode.

Abstract translation: 薄膜晶体管阵列面板包括基板，形成在基板上的栅极线，包括栅极电极，形成在栅极线上的栅极绝缘层，形成在栅极绝缘层上并包括薄膜晶体管的沟道的半导体 ，形成在半导体上的数据线，包括相对于薄膜晶体管的沟道形成在半导体上并与源电极相对的源电极和漏电极，其中薄膜晶体管的沟道覆盖两个侧表面 的栅电极。

公开(公告)号：US08497950B2

公开(公告)日：2013-07-30

申请号：US13614182

申请日：2012-09-13

Applicant: Young-Wook Lee ,  Jang-Soo Kim

Inventor： Young-Wook Lee ,  Jang-Soo Kim

IPC: G02F1/136

CPC classification number: H01L27/124 ,  G02F1/136209 ,  G02F1/136286 ,  G02F1/1365 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136222 ,  G02F2001/13629 ,  H01L27/1248

Abstract: A thin film transistor array panel includes a substrate; a plurality of gate lines that are formed on the substrate; a plurality of data lines that intersect the gate lines; a plurality of thin film transistors that are connected to the gate lines and the data lines; a plurality of color filters that are formed on upper parts of the gate lines, the data lines, and the thin film transistors; a common electrode that is formed on the color filters and that includes a transparent conductor; a passivation layer that is formed on an upper part of the common electrode; and a plurality of pixel electrodes that are formed on an upper part of the passivation layer and that are connected to a drain electrode of each of the thin film transistors.

公开(公告)号：US08187938B2

公开(公告)日：2012-05-29

申请号：US12754395

申请日：2010-04-05

Applicant: Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

Inventor： Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

IPC: H01L21/336

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Abstract translation: 一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽 在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出 衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

公开(公告)号：US20110175088A1

公开(公告)日：2011-07-21

申请号：US13004665

申请日：2011-01-11

Applicant: Jong In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

Inventor： Jong In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

IPC: H01L29/786 ,  H01L21/28

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract translation: 使用减少数量的掩模制造具有减少的缺陷的薄膜晶体管（TFT）基板。 TFT基板包括形成在基板上的栅极布线。 栅极布线包括栅电极。 在栅极布线上形成半导体图形。 在半导体图案上形成蚀刻停止图案。 数据布线包括形成在半导体图案上的源电极和蚀刻停止图案。 栅极布线和数据布线中的每一个包括在含铜层上形成的含铜层和缓冲层。

公开(公告)号：US20110168997A1

公开(公告)日：2011-07-14

申请号：US13006591

申请日：2011-01-14

Applicant: Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

Inventor： Young-Wook LEE ,  Woo-Geun LEE ,  Ki-Won KIM ,  Hyun-Jung LEE ,  Ji-Soo OH

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L27/124 ,  H01L21/76834 ,  H01L27/1225 ,  H01L27/1255 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/7869 ,  H01L29/78693

Abstract: A thin film transistor (TFT) array substrate and a manufacturing method thereof are provided. The TFT array substrate may include a gate line disposed on a substrate and including a gate line and a gate electrode, an oxide semiconductor layer pattern disposed on the gate electrode, a data line disposed on the oxide semiconductor layer pattern and including a source electrode and a drain electrode of a thin film transistor (TFT) together with the gate electrode, and a data line extending in a direction intersecting the gate line, and etch stop patterns disposed at an area where the TFT is formed between the source/drain electrodes and the oxide semiconductor layer pattern and at an area where the gate line and the data line overlap each other between the gate line and the data line.

Abstract translation: 提供薄膜晶体管（TFT）阵列基板及其制造方法。 TFT阵列基板可以包括设置在基板上的栅极线，包括栅极线和栅电极，设置在栅电极上的氧化物半导体层图案，设置在氧化物半导体层图案上的数据线，并且包括源电极和 薄膜晶体管（TFT）的漏电极和栅电极以及沿着与栅极线交叉的方向延伸的数据线，以及蚀刻停止图案，设置在源极/漏极之间形成TFT的区域，以及 氧化物半导体层图案和栅极线与数据线在栅极线与数据线之间重叠的区域。

公开(公告)号：US20090268134A1

公开(公告)日：2009-10-29

申请号：US12499212

申请日：2009-07-08

Applicant: Young-Wook Lee ,  Jang-Soo Kim ,  Kang-Woo Kim ,  Youn-Hak Jeong

Inventor： Young-Wook Lee ,  Jang-Soo Kim ,  Kang-Woo Kim ,  Youn-Hak Jeong

IPC: G02F1/1343 ,  H01L33/00 ,  G02F1/1333

CPC classification number: G02F1/136286 ,  G02F1/136209 ,  G02F2001/136222 ,  G02F2001/13629

Abstract: A liquid crystal display includes a first substrate, a plurality of gate lines formed on the first substrate, a plurality of data lines intersecting the gate lines, a plurality of thin film transistors connected to the gate lines and the data lines, a plurality of color filters formed on the gate lines, the data lines, and the thin film transistors, a plurality of first electrodes made of a transparent conductor formed on the color filters, and electrically connected to the thin film transistors, a first passivation layer formed on the first electrodes, a second electrode formed on the first passivation layer, and including a plurality of branch electrodes, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate.

Abstract translation: 液晶显示器包括第一基板，形成在第一基板上的多个栅极线，与栅极线交叉的多个数据线，连接到栅极线和数据线的多个薄膜晶体管，多个颜色 形成在栅极线，数据线和薄膜晶体管上的滤波器，形成在滤色器上的透明导体制成的多个第一电极，并与薄膜晶体管电连接;第一钝化层，形成在第一 电极，形成在第一钝化层上的第二电极，并且包括多个分支电极，面对第一基板的第二基板和设置在第一基板和第二基板之间的液晶层。

公开(公告)号：US20090251647A1

公开(公告)日：2009-10-08

申请号：US12361511

申请日：2009-01-28

Applicant: Young-Wook LEE ,  Gug-Rae Jo ,  Jang-Soo Kim ,  Jae-Hyoung Youn ,  Byoung-Joo Kim ,  Min-Uk Kim ,  Kyoung-Keun Son

Inventor： Young-Wook LEE ,  Gug-Rae Jo ,  Jang-Soo Kim ,  Jae-Hyoung Youn ,  Byoung-Joo Kim ,  Min-Uk Kim ,  Kyoung-Keun Son

IPC: G02F1/1335

CPC classification number: G02F1/136286 ,  G02F1/133514 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A display substrate includes a plurality of color filters, a gate line, an insulation layer, a data line and a plurality of pixel electrodes. The color filters are formed on a base substrate. The gate line is formed in a trench defined by at least one of the color filters and extended along a first direction. The insulation layer is formed on the color filters and the gate line. The data line is formed on the insulation layer to be extended along a second direction crossing the first direction. The pixel electrodes are formed on the base substrate having the data line formed thereon. Therefore, a metal wiring is formed in a trench defined by color filters, so that the resistance of the metal wiring may be decreased and an aperture ratio may be enhanced.

Abstract translation: 显示基板包括多个滤色器，栅极线，绝缘层，数据线和多个像素电极。 滤色器形成在基底基板上。 栅极线形成在由至少一个滤色器限定的沟槽中并且沿着第一方向延伸。 绝缘层形成在滤色器和栅极线上。 数据线形成在绝缘层上，沿着与第一方向交叉的第二方向延伸。 像素电极形成在其上形成有数据线的基底基板上。 因此，在由滤色器限定的沟槽中形成金属布线，从而可以降低金属布线的电阻，并且可以提高开口率。