公开(公告)号：US09754779B1

公开(公告)日：2017-09-05

申请号：US15048422

申请日：2016-02-19

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa

IPC: H01L21/44 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0217 ,  C23C16/045 ,  C23C16/345 ,  C23C16/45536 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31111

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

公开(公告)号：US11784043B2

公开(公告)日：2023-10-10

申请号：US17406919

申请日：2021-08-19

Applicant: ASM IP Holding B.V.

Inventor： Toshiya Suzuki ,  Viljami J. Pore ,  Shang Chen ,  Ryoko Yamada ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: H01L21/02

CPC classification number: H01L21/0228 ,  H01L21/0217 ,  H01L21/02208 ,  H01L21/02274

Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyl halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.

公开(公告)号：US11133181B2

公开(公告)日：2021-09-28

申请号：US16543917

申请日：2019-08-19

Applicant: ASM IP Holding B.V.

Inventor： Toshiya Suzuki ,  Viljami J. Pore ,  Shang Chen ,  Ryoko Yamada ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: H01L21/02

Abstract: Methods of forming silicon nitride thin films on a substrate in a reaction space under high pressure are provided. The methods can include a plurality of plasma enhanced atomic layer deposition (PEALD) cycles, where at least one PEALD deposition cycle comprises contacting the substrate with a nitrogen plasma at a process pressure of 20 Torr to 500 Torr within the reaction space. In some embodiments the silicon precursor is a silyly halide, such as H2SiI2. In some embodiments the processes allow for the deposition of silicon nitride films having improved properties on three dimensional structures. For example, such silicon nitride films can have a ratio of wet etch rates on the top surfaces to the sidewall of about 1:1 in dilute HF.

公开(公告)号：US10811256B2

公开(公告)日：2020-10-20

申请号：US16161744

申请日：2018-10-16

Applicant: ASM IP Holding B.V.

Inventor： Mitsuya Utsuno ,  Tomohiro Kubota ,  Dai Ishikawa

IPC: H01L21/027 ,  H01L21/311 ,  H01J37/32

Abstract: Methods for etching a carbon-containing feature are provided. The methods may include: providing a substrate having a carbon-containing feature formed thereon in a reaction space; supplying helium gas and an oxidizing to the reaction space; generating a plasma within the reaction space from a gas mixture comprising helium gas and the oxidizing gas; and anisotropically etching the carbon-containing feature utilizing the plasma to cause lateral etching of the carbon-containing feature.

公开(公告)号：US10658181B2

公开(公告)日：2020-05-19

申请号：US15900425

申请日：2018-02-20

Applicant: ASM IP Holding B.V.

Inventor： Toshihisa Nozawa ,  Dai Ishikawa ,  Tomohiro Kubota

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768

Abstract: A method of spacer-defined direct patterning in semiconductor fabrication includes: providing a photoresist structure having a target width of lines; trimming the photoresist structures such that a width of each trimmed photoresist structure is smaller than the target width; depositing an oxide film on the template, thereby entirely covering with the oxide film an exposed top surface of the template and the trimmed photoresist structures; etching the oxide film-covered template to remove an unwanted portion of the oxide film without removing the trimmed photoresist structures so as to form vertical spacers isolated from each other, each spacer substantially maintaining the target width and being constituted by the trimmed photoresist structures and a vertical portion of the oxide film covering sidewalls of the trimmed photoresist structures; and etching the spacer-formed template to transfer a pattern constituted by the spacers to the template.

公开(公告)号：US10468251B2

公开(公告)日：2019-11-05

申请号：US15650686

申请日：2017-07-14

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa ,  Toshiharu Watarai

IPC: H01L21/033 ,  H01L21/02 ,  H01L21/311 ,  H01L21/308 ,  C23C16/455 ,  C23C16/34

Abstract: A method of forming spacers for spacer-defined multiple pattering (SDMP), includes: depositing a pattern transfer film by PEALD on the entire patterned surface of a template using halogenated silane as a precursor and nitrogen as a reactant at a temperature of 200° C. or less, which pattern transfer film is a silicon nitride film; dry-etching the template using a fluorocarbon as an etchant, and thereby selectively removing a portion of the pattern transfer film formed on a top of a core material and a horizontal portion of the pattern transfer film while leaving the core material and a vertical portion of the pattern transfer film as a vertical spacer, wherein a top of the vertical spacer is substantially flat; and dry-etching the core material, whereby the template has a surface patterned by the vertical spacer on a underlying layer.

公开(公告)号：US20190148224A1

公开(公告)日：2019-05-16

申请号：US15815483

申请日：2017-11-16

Applicant: ASM IP Holding B.V.

Inventor： Aurélie Kuroda ,  Akiko Kobayashi ,  Dai Ishikawa

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532

Abstract: A method of selectively depositing a capping layer structure on a semiconductor device structure is disclosure. The method may include; providing a partially fabricated semiconductor device structure comprising a surface including a metallic interconnect material, a metallic barrier material, and a dielectric material. The method may also include; selectively depositing a first metallic capping layer over the metallic barrier material and over the metallic interconnect material relative to the dielectric material; and selectively depositing a second metallic capping layer over the first metallic capping layer relative to the dielectric material. Semiconductor device structures including a capping layer structure are also disclosed.

公开(公告)号：US20170358482A1

公开(公告)日：2017-12-14

申请号：US15622510

申请日：2017-06-14

Applicant: ASM IP HOLDING B.V.

Inventor： Shang Chen ,  Toshiharu Watarai ,  Takahiro Onuma ,  Dai Ishikawa ,  Kunitoshi Namba

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285

CPC classification number: H01L21/7685 ,  H01L21/28562 ,  H01L21/28568 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/76823 ,  H01L21/76826 ,  H01L21/76868 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53266

Abstract: Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic layers are selectively deposited on a first metallic surface relative to a second surface comprising silicon. In some embodiments the reaction chamber in which the selective deposition occurs may optionally be passivated prior to carrying out the selective deposition process. In some embodiments selectivity of above about 50% or even about 90% is achieved.

公开(公告)号：US20170250068A1

公开(公告)日：2017-08-31

申请号：US15592730

申请日：2017-05-11

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa ,  Eiichiro Shiba ,  Shinya Ueda ,  Taishi Ebisudani ,  SeungJu Chun ,  YongMin Yoo ,  YoonKi Min ,  SeYong Kim ,  JongWan Choi

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0217 ,  H01J2237/3347 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/31111

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

公开(公告)号：US20170243734A1

公开(公告)日：2017-08-24

申请号：US15048422

申请日：2016-02-19

Applicant: ASM IP Holding B.V.

Inventor： Dai Ishikawa ,  Atsuki Fukazawa

IPC: H01L21/02 ,  H01L21/311

CPC classification number: H01L21/0217 ,  C23C16/045 ,  C23C16/345 ,  C23C16/45536 ,  C23C16/505 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31111

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.