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    Selective insertion of clock mismatch compensation symbols in signal transmissions based on a receiver's compensation capability
    21.
    发明授权
    Selective insertion of clock mismatch compensation symbols in signal transmissions based on a receiver's compensation capability 有权
    基于接收机的补偿能力，在信号传输中选择性地插入时钟失配补偿符号

    公开(公告)号：US09213355B2

    公开(公告)日：2015-12-15

    申请号：US13670086

    申请日：2012-11-06

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Gordon F. Caruk ,  Gerald R. Talbot

    IPC: G06F1/00 ,  G06F5/06 ,  H04L7/00 ,  H04L7/04

    CPC classification number: G06F1/00 ,  G06F1/04 ,  G06F5/06 ,  H04L7/00 ,  H04L7/005 ,  H04L2007/045

    Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.

    Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。

    METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONITORING CIRCUIT
    22.
    发明申请
    METHOD AND APPARATUS FOR POWER-UP DETECTION FOR AN ELECTRICAL MONITORING CIRCUIT 有权
    用于电力监测电路上电检测的方法和装置

    公开(公告)号：US20150130519A1

    公开(公告)日：2015-05-14

    申请号：US14518591

    申请日：2014-10-20

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

    IPC: H03K3/01

    CPC classification number: H03K17/22

    Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

    Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。

    RECEIVER EQUALIZATION CIRCUITRY USING VARIABLE TERMINATION AND T-COIL
    23.
    发明公开
    RECEIVER EQUALIZATION CIRCUITRY USING VARIABLE TERMINATION AND T-COIL 审中-公开

    公开(公告)号：US20230308132A1

    公开(公告)日：2023-09-28

    申请号：US17705022

    申请日：2022-03-25

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Dean E. Gonzales ,  Edoardo Prete ,  Milam Paraschou ,  Mark Chirachanchai ,  Gerald R. Talbot

    IPC: H04B3/14 ,  H04B3/26 ,  H04B3/46

    CPC classification number: H04B3/141 ,  H04B3/145 ,  H04B3/26 ,  H04B3/46 ,  H01F17/08

    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. In order to better handle noise issues when using single-ended signaling, one or more of the receivers include equalization circuitry and termination circuitry. The termination circuitry prevents reflection on a corresponding transmission line ending at a corresponding receiver. The equalization circuitry uses a bridged T-coil circuit to provide continuous time linear equalization (CTLE) with no feedback loop. The equalization circuitry performs equalization by providing a high-pass filter that offsets the low-pass characteristics of a corresponding transmission line. A comparator of the receiver receives the input signal and compares it to a reference voltage. The placement of the comparator and the ratio of the inductances of the inductors of the bridged T-coil circuit are based on whether the receiver includes self-diagnostic circuitry.

    Low power VTT generation mechanism for receiver termination
    25.
    发明授权
    Low power VTT generation mechanism for receiver termination 有权

    公开(公告)号：US10692545B2

    公开(公告)日：2020-06-23

    申请号：US16140356

    申请日：2018-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

    IPC: G11C7/10 ,  G11C5/14 ,  G11C11/4074 ,  H04L25/02 ,  H03K17/687

    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

    LOW POWER VTT GENERATION MECHANISM FOR RECEIVER TERMINATION
    26.
    发明申请
    LOW POWER VTT GENERATION MECHANISM FOR RECEIVER TERMINATION 审中-公开

    公开(公告)号：US20200098399A1

    公开(公告)日：2020-03-26

    申请号：US16140356

    申请日：2018-09-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Balwinder Singh ,  Gerald R. Talbot ,  Alushulla Jack Ambundo ,  Edoardo Prete ,  Thomas H. Likens, III ,  Michael A. Margules

    IPC: G11C5/14 ,  H03K17/687 ,  H04L25/02 ,  G11C11/4074

    Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A termination voltage generator includes an inverter-based chopper circuit, which uses a first group of an even number of serially connected inverters coupled between the output node of the chopper circuit and the gate terminal of an output pmos transistor. Additionally, a second group of an even number of serially connected inverters is coupled between the output node and the gate terminal of an output nmos transistor. A replica inverter includes two serially connected pmos transistors and two serially connected nmos transistors. Each of one pmos transistor and one nmos transistor receives a generated voltage set as the expected value of the termination voltage. Each of the other pmos transistor and nmos transistor receives an output based on a comparison between the expected value to the output of the replica inverter.

    Active equalizing negative resistance amplifier for bi-directional bandwidth extension
    27.
    发明授权
    Active equalizing negative resistance amplifier for bi-directional bandwidth extension 有权

    公开(公告)号：US10122392B2

    公开(公告)日：2018-11-06

    申请号：US15240549

    申请日：2016-08-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Milam Paraschou ,  Gerald R. Talbot ,  Dean E. Gonzales

    IPC: H04B1/38 ,  H04L5/16 ,  H04B1/04 ,  H03F3/45

    Abstract: Systems, apparatuses, and methods for implementing a negative resistance circuit for bandwidth extension are disclosed. Within a feedback path of a differential signal path, capacitors are placed on the inputs and outputs of a fully differential amplifier connecting to the differential signal path. In one embodiment, a circuit includes a fully differential amplifier and four capacitors. A first capacitor is coupled between a first signal path and a non-inverting input terminal of the amplifier and a second capacitor is coupled between the first signal path and a non-inverting output terminal of the amplifier. A third capacitor is coupled between a second signal path and an inverting input terminal of the amplifier and a fourth capacitor is coupled between the second signal path and an inverting output terminal of the amplifier. The first and second signal paths carry a differential signal.

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