公开(公告)号：US06730989B1

公开(公告)日：2004-05-04

申请号：US09596130

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L23/5382 ,  H01L23/50 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。

公开(公告)号：US09666238B2

公开(公告)日：2017-05-30

申请号：US14114725

申请日：2012-05-11

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C5/02 ,  G11C5/06 ,  H01L23/48 ,  H01L27/108 ,  H01L25/065

CPC分类号： G11C5/063 ,  G11C5/025 ,  H01L23/481 ,  H01L25/0657 ,  H01L27/10897 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory stack includes a number of memory dies including a master die and one or more slave dies. The slave die can be converted to a master die by further processing. The slave die includes a memory core having memory cell arrays. The slave die also includes first and second metal layers that form first and second distribution lines in the memory core, respectively. An interface circuit in the slave die is decoupled from the first and second metal layers.

公开(公告)号：US20120327726A1

公开(公告)日：2012-12-27

申请号：US13578864

申请日：2010-12-01

申请人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

发明人： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C7/00

CPC分类号： G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

摘要： A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

摘要翻译： 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20120170356A1

公开(公告)日：2012-07-05

申请号：US13393216

申请日：2010-07-30

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C11/24 ,  H01L21/8242

CPC分类号： G11C11/401 ,  H01L27/10885 ,  H01L27/10888

摘要： A dynamic random access memory (DRAM) device has a hierarchical bitline structure with local bitlines and global bitlines formed on different metal layers. The local bitlines are separated into a plurality of local bitline sections, and bitline isolation switches are configured to connect or disconnect the local bitline sections to or from the global bitlines. As a result, the local bitlines with higher per-length capacitance can be made shorter, since the global bitline with lower per-length capacitance is used to route the signal from the cell capacitances of the memory cells to the remote sense amplifiers.

摘要翻译： 动态随机存取存储器（DRAM）器件具有分层位线结构，其中局部位线和在不同金属层上形成的全局位线。 局部位线被分成多个本地位线部分，并且位线隔离开关被配置为将本地位线部分连接到全局位线或从全局位线断开连接。 结果，由于具有较低的每长度电容的全局位线用于将来自存储器单元的单元电容的信号路由到远程读出放大器，所以可以使具有较高每个长度电容的局部位线更短。

公开(公告)号：US20120166753A1

公开(公告)日：2012-06-28

申请号：US13394533

申请日：2010-08-23

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G11C7/1012 ,  G11C7/1045 ,  G11C11/4087 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/105

摘要： A memory device has a storage array having a plurality of accessible memory banks and a configurable first set of memory segments. The plurality of accessible memory banks include a second set of memory segments. During a first mode of operation, the first set of memory segments is configured to be an additional accessible memory bank. During a second mode of operation, a pair of memory segments in the first set of memory segments are configured to be an additional set of memory segments in each of the plurality of accessible memory banks.

摘要翻译： 存储器件具有存储阵列，其具有多个可存取存储体和可配置的第一组存储器段。 多个可存储存储体包括第二组存储器段。 在第一操作模式期间，第一组存储器段被配置为附加的可访问存储体。 在第二操作模式期间，第一组存储器段中的一对存储器段被配置为在多个可存取存储体的每一个中的另外一组存储器段。

公开(公告)号：US20110185257A1

公开(公告)日：2011-07-28

申请号：US12693837

申请日：2010-01-26

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： H03M13/05 ,  G06F11/10 ,  G06F12/02

CPC分类号： G06F11/10 ,  G06F11/1048 ,  H03M13/19 ,  H03M13/2909

摘要： A semiconductor memory chip including error correction circuitry configured to receive data words from an external device, each data word comprising a binary number of data bits, and configured to error encode each data word to form a corresponding coded word comprising a non-binary number of data bits including the data bits of the data word and a plurality of error correction code bits. At least one memory cell array is configured to receive and store the coded word and partitioned based on the non-binary number of bits of the coded word so as to have a non-binary number of wordlines and provide the memory chip with an aspect ratio other than a 2:1 aspect ratio.

摘要翻译： 一种半导体存储器芯片，包括错误校正电路，其被配置为从外部设备接收数据字，每个数据字包括二进制数量的数据位，并且被配置为对每个数据字进行错误编码以形成相应的编码字，所述对应的编码字包括非二进制数 数据位包括数据字的数据位和多个纠错码位。 至少一个存储单元阵列被配置为基于编码字的非二进制位数来接收和存储编码字并分区，以便具有非二进制数字的字线，并为存储器芯片提供宽高比 除了2：1的纵横比。

公开(公告)号：US20080273407A1

公开(公告)日：2008-11-06

申请号：US11744790

申请日：2007-05-04

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C7/24

CPC分类号： G11C29/02 ,  G11C11/401 ,  G11C29/025 ,  G11C29/83 ,  G11C2029/1202

摘要： Method and apparatus for testing for a short between a wordline being tested and a bitline in a memory device. The method includes applying a first voltage to the bitline using a first voltage source and applying a second voltage to the wordline being tested using a second voltage source. The method further includes disconnecting the wordline being tested from the second voltage source; and after disconnecting the wordline being tested from the second voltage source, activating the wordline being tested, thereby connecting the wordline being tested to a wordline power supply line. A determination is made of whether a voltage of the wordline power supply line indicates a short between the wordline being tested and the bitline. The determination is based on the voltage of the wordline power supply line relative to the first voltage and the second voltage.

摘要翻译： 在被测试的字线和存储器件中的位线之间测试短路的方法和装置。 该方法包括使用第一电压源向位线施加第一电压，并使用第二电压源向被测试的字线施加第二电压。 该方法还包括将正在测试的字线与第二电压源断开连接; 并且在断开正在测试的字线与第二电压源之间，激活被测试的字线，从而将被测试的字线连接到字线电源线。 确定字线电源线的电压是否表示正在被测试的字线和位线之间的短路。 该确定基于字线电源线相对于第一电压和第二电压的电压。

公开(公告)号：US07227799B2

公开(公告)日：2007-06-05

申请号：US11118036

申请日：2005-04-29

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： G11C7/00

CPC分类号： G11C11/4094 ,  G11C7/065 ,  G11C7/12 ,  G11C11/4091

摘要： A sense amplifier comprises a transistor configured to be switched with a column select line to pass a bit line equalization voltage, an array equalize device coupled to the transistor for receiving the bit line equalization voltage, a sense amplifier equalize device, a multiplexer coupled between the sense amplifier equalize device and the array equalize device, and a cross-coupled amplifier latch coupled to the sense amplifier equalize device.

摘要翻译： 读出放大器包括晶体管，其被配置为与列选择线切换以通过位线均衡电压;耦合到晶体管的阵列均衡器件，用于接收位线均衡电压;读出放大器均衡器件; 读出放大器均衡器件和阵列均衡器件，以及耦合到读出放大器的交叉耦合放大器锁存器来均衡器件。

公开(公告)号：US20050280083A1

公开(公告)日：2005-12-22

申请号：US10873010

申请日：2004-06-22

申请人： Thomas Vogelsang

发明人： Thomas Vogelsang

IPC分类号： H01L27/092 ,  H01L29/76 ,  H03K3/00 ,  H03K19/00

CPC分类号： H03K19/0013 ,  H01L27/0925 ,  H01L27/0928 ,  Y10S257/901

摘要： An integrated circuit device including a plurality of MOSFETs of similar type and geometry is formed on a substrate with an ohmic contact, and an adjustable voltage source on the die utilizing clearable fuses is coupled between the ohmic contact and the sources of the MOSFETs. After die processing, a post-processing test is performed to measure an operating characteristic of the die such as leakage current or switching speed, and an external voltage source is applied and adjusted to control the operating characteristic. The on-die fuses are then cleared to adjust the on-die voltage source to match the externally applied voltage. The operating characteristic may be determined by including a test circuit on the die to exhibit the operating characteristic such as a ring oscillator frequency. This approach to controlling manufacturing-induced device performance variations is well suited to efficient manufacture of small feature-size circuits such as DRAMs.

摘要翻译： 在具有欧姆接触的衬底上形成包括具有相似类型和几何形状的多个MOSFET的集成电路器件，并且使用可清除熔丝的管芯上的可调电压源耦合在欧姆接触和MOSFET的源极之间。 在模具处理之后，进行后处理试验以测量管芯的工作特性，例如漏电流或开关速度，施加外部电压源并进行调整以控制工作特性。 然后清除管芯内保险丝以调整片上电压源以匹配外部施加的电压。 操作特性可以通过在芯片上包括测试电路来表现出诸如环形振荡器频率的工作特性来确定。 用于控制制造引起的器件性能变化的这种方法非常适合于诸如DRAM的小型特征尺寸电路的有效制造。

公开(公告)号：US06815803B1

公开(公告)日：2004-11-09

申请号：US09596129

申请日：2000-06-16

申请人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

发明人： Manfred Reithinger ,  Mike Killian ,  Gerd Frankowsky ,  Oliver Kiehl ,  Gerhard Mueller ,  Ernst Stahl ,  Hartmud Terletzki ,  Thomas Vogelsang

IPC分类号： H01L23544

CPC分类号： H01L25/18 ,  H01L23/50 ,  H01L23/5382 ,  H01L27/105 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor packaging arrangement, or module, includes a printed circuit board having an electrical interconnect thereon and a semiconductor package mounted to the printed circuit board. The semiconductor package includes a fractional portion of a semiconductor wafer having a plurality of integrated circuit chips thereon, such chips being separated by regions in the fractional portion of the wafer. The fractional portion of the wafer has a plurality of electrical contacts electrically connected to the chips. The package also includes a dielectric member having an electrical conductor thereon. The electrical conductor are electrically connected to the plurality of electrical contacts of the plurality of chips to electrically interconnect such plurality of chips with portions of the electrical conductor spanning the regions in the fractional portion of the wafer. A connector is provided for electrically connecting the electrical conductor of the package to the electrical interconnect of the printed circuit board.

摘要翻译： 半导体封装装置或模块包括其上具有电互连的印刷电路板和安装到印刷电路板的半导体封装。 半导体封装包括其上具有多个集成电路芯片的半导体晶片的分数部分，这些芯片由晶片的分数部分中的区域分隔开。 晶片的分数部分具有电连接到芯片的多个电触点。 封装还包括其上具有电导体的电介质构件。 电导体电连接到多个芯片的多个电触头，以将这些多个芯片与跨越晶片的分数部分中的区域的电导体的部分电互连。 提供一种用于将封装的电导体电连接到印刷电路板的电互连的连接器。