公开(公告)号：US20160292094A1

公开(公告)日：2016-10-06

申请号：US14676174

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Brijesh Tripathi ,  Kiran Kattel ,  Rakesh L. Notani ,  Fabien S. Faure ,  Sukalpa Biswas ,  Kai Lun Hsiung ,  Neeraj Parik ,  Venkata Ramana Malladi ,  Shiva Kumar ,  Chaitanya Polapragada ,  Allen Kim

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1689 ,  Y02D10/14

Abstract: An apparatus and method for encoding data are disclosed that may allow for performing periodic calibration operations on a communication link. A controller may determine multiple possible values for a reference voltage used with the communication link based on an initial value. Calibration operations may be performed using each possible value, and the results of the operations scored based on the width of data eyes measured during the calibration operations. The controller may then select a new value for the reference voltage from the multiple possible values dependent upon the scores of each of the multiple possible values.

Abstract translation: 公开了一种用于编码数据的装置和方法，其可以允许在通信链路上执行周期性校准操作。 控制器可以基于初始值来确定与通信链路一起使用的参考电压的多个可能值。 可以使用每个可能的值执行校准操作，并且基于在校准操作期间测量的数据眼睛的宽度来评估操作的结果。 然后，控制器可以根据多个可能值中的每一个的分数从多个可能值中选择参考电压的新值。

公开(公告)号：US12118249B2

公开(公告)日：2024-10-15

申请号：US18497883

申请日：2023-10-30

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Shane J. Keil ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Tao Zhang

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0644 ,  G06F3/0673 ,  G06F13/1605

Abstract: Systems, apparatuses, and methods for addressing bank hotspotting are described. A computing system includes a memory controller with an arbiter for determining how to arbitrate access to one or more memory device(s) for received requests. The arbiter categorizes each request in a manner that helps to ensure fair virtual channel distribution across the banks of the memory device(s). The category system includes bank hotspotting functions to give banks that have more requests more chances to go over banks with fewer requests. The category system is implemented proportionally with more category credits given to banks with higher bank depths within the virtual channel.

公开(公告)号：US20240211151A1

公开(公告)日：2024-06-27

申请号：US18596046

申请日：2024-03-05

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Jingkui Zheng ,  David A. Knopf ,  Satish B. Dulam ,  Kai Lun Hsiung ,  Venkata Ramana Malladi ,  Rahul Ranjan

IPC: G06F3/06 ,  G11C7/22

CPC classification number: G06F3/0632 ,  G06F3/0614 ,  G06F3/0658 ,  G06F3/0673 ,  G11C7/22 ,  G11C2207/2254

Abstract: An apparatus for performing a write data strobe concurrent with a reference voltage calibration is disclosed. A memory controller circuit is configured to convey a write clock signal to a memory. The memory controller circuit includes a calibration circuit configured to send a first command to memory to initiate a calibration of the write clock signal and, after an amount of time has elapsed, receive a calibration value from the memory. The memory controller further includes a delay circuit configured to apply a delay to the write clock signal, wherein the calibration circuit is configured to complete calibration of the write clock signal by adjusting the delay applied to the write clock signal in accordance with the calibration value. The calibration circuit is further configured to perform a reference voltage calibration concurrent with the calibration of the write clock signal.

公开(公告)号：US10678478B2

公开(公告)日：2020-06-09

申请号：US16112624

申请日：2018-08-24

Applicant: Apple Inc.

Inventor： Shane J. Keil ,  Gregory S. Mathews ,  Lakshmi Narasimha Murthy Nukala ,  Thejasvi Magudilu Vijayaraj ,  Kai Lun Hsiung ,  Yanzhe Liu ,  Sukalpa Biswas

IPC: G06F3/06

Abstract: An embodiment of an apparatus includes a memory circuit and a memory controller circuit. The memory controller circuit may include a write request queue. The memory controller circuit may be configured to receive a memory request to access the memory circuit and determine if the memory request includes a read request or a write request. A received read request may be scheduled for execution, while a received write request may be stored in the write request queue. The memory controller circuit may reorder scheduled memory requests based on achieving a specified memory access efficiency and based on a number of write requests stored in the write request queue.

公开(公告)号：US20190385670A1

公开(公告)日：2019-12-19

申请号：US16012427

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Lakshmi Narasimha Murthy Nukala ,  Kai Lun Hsiung ,  Sukalpa Biswas ,  Yanzhe Liu

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G06F13/16

Abstract: A method and apparatus for optimizing calibrations of a memory subsystem is disclosed. A memory controller of a memory subsystem includes a memory interface suitable for coupling to a DRAM having a plurality of banks. The memory controller includes a state machine the state machine may initiate calibration of circuitry within the memory controller. Responsive to initiating the calibration, the state machine also causes a refresh command to be transmitted to the DRAM. The calibration is then performed concurrent with the refresh of the DRAM. Subsequent to transmitting the refresh command, the state machine causes the memory interface to be placed into a low power state.

公开(公告)号：US20190385669A1

公开(公告)日：2019-12-19

申请号：US16012366

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Kai Lun Hsiung ,  Peter Fu

IPC: G11C11/406 ,  G11C8/18 ,  G11C5/14

Abstract: A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.

公开(公告)号：US10510396B1

公开(公告)日：2019-12-17

申请号：US16012366

申请日：2018-06-19

Applicant: Apple Inc.

Inventor： Rakesh L. Notani ,  Kai Lun Hsiung ,  Peter Fu

IPC: G11C7/00 ,  G11C11/406 ,  G11C5/14 ,  G11C8/18

Abstract: A memory controller includes a state machine that initiates a memory refresh of a DRAM (having a number of banks) by sending thereto a refresh command. Responsive to receiving the command, the DRAM may perform a per-bank refresh in which individual ones of the banks are refreshed in succession, one at a time. Upon receiving a high priority transaction, a determination is made as to the number of memory banks that have currently been refreshed in the per-bank refresh. If the number of banks refreshed is less than a threshold value, the per-bank refresh is aborted.

公开(公告)号：US10175905B2

公开(公告)日：2019-01-08

申请号：US15263833

申请日：2016-09-13

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Liang Deng ,  Kai Lun Hsiung ,  Manu Gulati ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Venkata Ramana Malladi ,  Gregory S. Mathews ,  Enming Zheng ,  Fabien S. Faure

IPC: G06F1/32 ,  G06F3/06 ,  G06F1/08 ,  G06F13/16 ,  G06F13/42

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

公开(公告)号：US09928890B2

公开(公告)日：2018-03-27

申请号：US15249962

申请日：2016-08-29

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Rakesh L. Notani ,  Kai Lun Hsiung ,  Alma L. Juarez Dominguez

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/10 ,  G11C7/222 ,  G11C11/401 ,  G11C29/023 ,  G11C29/028 ,  G11C29/12015

Abstract: A system and method for calibrating memory using credit-based segmentation control is disclosed. A memory and a memory controller coupled thereto. The memory controller includes a calibration circuit configured to calibrate a data strobe signal conveyed to/from the memory. The calibration may be subdivided, in time, into a number of segments. The memory controller also includes a credit circuit configured to provide a condition code to the calibration circuit. The condition code may be indicative of an amount of time a request has been pending, or how many request are pending. If the condition code indicates that a request has been pending for more than a certain amount of time, the calibration may be terminated.

公开(公告)号：US20220270664A1

公开(公告)日：2022-08-25

申请号：US17181979

申请日：2021-02-22

Applicant: Apple Inc.

Inventor： Robert E. Jeter ,  Kai Lun Hsiung ,  Rakesh L. Notani ,  Venkata Ramana Malladi ,  John H. Kelm ,  Taehyun Kim

IPC: G11C11/4074 ,  G11C11/4096 ,  G11C11/4076 ,  G06F3/06

Abstract: A method and apparatus for selective reference voltage calibration in a memory subsystem is disclosed. A memory subsystem includes a memory coupled to a memory controller. The memory controller may operate in one of a number of different performance states. The memory controller further includes a calibration circuit configured to perform reference voltage calibrations for the various ones of the performance states to determine corresponding reference voltages. For a performance state change from an initial performance state to a final performance state, via an intermediate performance state, the memory controller is configured to transition to the intermediate performance state without causing the calibration circuit to perform a reference voltage calibration in that state. Thereafter, the memory controller transitions to the final performance state.