公开(公告)号：US12007920B2

公开(公告)日：2024-06-11

申请号：US18301837

申请日：2023-04-17

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

CPC classification number: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US20230333851A1

公开(公告)日：2023-10-19

申请号：US18336704

申请日：2023-06-16

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

IPC: G06F9/30 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/30043 ,  G06F12/0238 ,  G06F12/0875 ,  G06F9/30047 ,  G06F9/3834 ,  G06F9/30101

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

公开(公告)号：US20230251985A1

公开(公告)日：2023-08-10

申请号：US18301837

申请日：2023-04-17

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

CPC classification number: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US11720360B2

公开(公告)日：2023-08-08

申请号：US17469504

申请日：2021-09-08

Applicant: Apple Inc.

Inventor： Jeff Gonion ,  John H. Kelm ,  James Vash ,  Pradeep Kanapathipillai ,  Mridul Agarwal ,  Gideon N. Levinsky ,  Richard F. Russo ,  Christopher M. Tsay

IPC: G06F9/30 ,  G06F12/02 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30101 ,  G06F9/3834 ,  G06F12/0238 ,  G06F12/0875

Abstract: Techniques are disclosed relating to data synchronization barrier operations. A system includes a first processor that may receive a data barrier operation request from a second processor include in the system. Based on receiving that data barrier operation request from the second processor, the first processor may ensure that outstanding load/store operations executed by the first processor that are directed to addresses outside of an exclusion region have been completed. The first processor may respond to the second processor that the data barrier operation request is complete at the first processor, even in the case that one or more load/store operations that are directed to addresses within the exclusion region are outstanding and not complete when the first processor responds that the data barrier operation request is complete.

公开(公告)号：US11630789B2

公开(公告)日：2023-04-18

申请号：US17246311

申请日：2021-04-30

Applicant: Apple Inc.

Inventor： Jeffrey E. Gonion ,  Charles E. Tucker ,  Tal Kuzi ,  Richard F. Russo ,  Mridul Agarwal ,  Christopher M. Tsay ,  Gideon N. Levinsky ,  Shih-Chieh Wen ,  Lior Zimet

IPC: G06F13/24 ,  G06F1/26

Abstract: An interrupt delivery mechanism for a system includes and interrupt controller and a plurality of cluster interrupt controllers coupled to respective pluralities of processors in an embodiment. The interrupt controller may serially transmit an interrupt request to respective cluster interrupt controllers, which may acknowledge (Ack) or non-acknowledge (Nack) the interrupt based on attempting to deliver the interrupt to processors to which the cluster interrupt controller is coupled. In a soft iteration, the cluster interrupt controller may attempt to deliver the interrupt to processors that are powered on, without attempting to power on processors that are powered off. If the soft iteration does not result in an Ack response from one of the plurality of cluster interrupt controllers, a hard iteration may be performed in which the powered-off processors may be powered on.

公开(公告)号：US11468168B1

公开(公告)日：2022-10-11

申请号：US15484439

申请日：2017-04-11

Applicant: Apple Inc.

Inventor： Conrado Blasco ,  Ian D. Kountanis ,  Douglas C. Holman ,  Sean M. Reynolds ,  Richard F. Russo

IPC: G06F21/56 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875

Abstract: Systems, apparatuses, and methods for efficient handling of subroutine epilogues. When an indirect control transfer instruction corresponding to a procedure return for a subroutine is identified, the return address and a signature are retrieved from one or more of a return address stack and the memory stack. An authenticator generates a signature based on at least a portion of the retrieved return address. While the signature is being generated, instruction processing speculatively continues. No instructions are permitted to commit yet. The generated signature is later compared to a copy of the signature generated earlier during the corresponding procedure call. A mismatch causes an exception.

公开(公告)号：US10990159B2

公开(公告)日：2021-04-27

申请号：US15496290

申请日：2017-04-25

Applicant: Apple Inc.

Inventor： Bernard Joseph Semeria ,  John H. Mylius ,  Pradeep Kanapathipillai ,  Richard F. Russo ,  Shih-Chieh Wen ,  Richard H. Larson

IPC: G06F9/38 ,  G06F3/06 ,  G06F1/3287 ,  G06F1/3228 ,  G06F1/3206 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for retaining architected state for relatively frequent switching between sleep and active operating states are described. A processor receives an indication to transition from an active state to a sleep state. The processor stores a copy of a first subset of the architected state information in on-die storage elements capable of retaining storage after power is turned off. The processor supports programmable input/output (PIO) access of particular stored information during the sleep state. When a wakeup event is detected, circuitry within the processor is powered up again. A boot sequence and recovery of architected state from off-chip memory are not performed. Rather than fetch from a memory location pointed to by a reset base address register, the processor instead fetches an instruction from a memory location pointed to by a restored program counter of the retained subset of the architected state information.

公开(公告)号：US10037073B1

公开(公告)日：2018-07-31

申请号：US15273925

申请日：2016-09-23

Applicant: Apple Inc.

Inventor： Edvin Catovic ,  Rajat Goel ,  Richard F. Russo ,  Matthew R. Johnson ,  Shingo Suzuki ,  Pradeep Kanapathipillai ,  Raghava Rao V. Denduluri ,  Pankaj Lnu

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/3243

Abstract: A processor includes an instruction issue circuit, and high-utilization and low-utilization execution unit circuits coupled to execute instructions received from the instruction issue unit. On average, utilization of the low-utilization execution unit circuit is lower than utilization of the high-utilization execution unit circuit. The processor also includes a retention circuit coupled to a different power domain than the low-utilization execution unit circuit, and a power management circuit. The power management circuit may be configured to detect that inactivity of the low-utilization execution unit circuit satisfies a threshold inactivity level; upon detecting that the threshold inactivity level is satisfied, cause architecturally-visible state of the low-utilization execution unit circuit to be copied to the retention circuit; and subsequent to copying of the architecturally-visible state to the retention circuit, cause the low-utilization execution unit circuit to enter a power-off state, where the retention circuit retains stored data during the power-off state.

公开(公告)号：US20160147290A1

公开(公告)日：2016-05-26

申请号：US14548912

申请日：2014-11-20

Applicant: Apple Inc.

Inventor： David J. Williamson ,  Gerard R. Williams, III ,  James N. Hardage, Jr. ,  Richard F. Russo

IPC: G06F1/32

CPC classification number: G06F1/3293 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/122 ,  Y02D10/171

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, and another core may be implemented at a lower maximum performance, but may be optimized for efficiency. Additionally, in some embodiments, some features of the instruction set architecture implemented by the processor may be implemented in only one of the cores that make up the processor. If such a feature is invoked by a code sequence while a different core is active, the processor may swap cores to the core the implements the feature. Alternatively, an exception may be taken and an exception handler may be executed to identify the feature and activate the corresponding core.

Abstract translation: 在一个实施例中，集成电路可以包括一个或多个处理器。 每个处理器可以包括多个处理器核心，并且每个核心具有不同的设计/实现和性能水平。 例如，可以实现用于高性能的核心，并且可以以较低的最大性能来实现另一个核心，但是可以针对效率进行优化。 另外，在一些实施例中，由处理器实现的指令集架构的一些特征可以仅在构成处理器的一个核中实现。 如果在不同核心处于活动状态时由代码序列调用这样的特征，则处理器可以将核心交换到核心来实现该特征。 或者，可以采取异常并且可以执行异常处理程序来识别特征并激活相应的核。