公开(公告)号：US6096589A

公开(公告)日：2000-08-01

申请号：US22757

申请日：1998-02-12

Applicant: John K. Lee ,  Behnam Moradi ,  Michael J. Westphal

Inventor： John K. Lee ,  Behnam Moradi ,  Michael J. Westphal

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8249

CPC classification number: H01L21/82385 ,  H01L27/0922 ,  H01L29/1087 ,  H01L29/4916 ,  H01L29/7835

Abstract: CMOS devices and process for fabricating low voltage, high voltage, or both low voltage and high voltage CMOS devices are disclosed. According to the process, p-channel stops and source/drain regions of PMOS devices are implanted into a substrate in a single step. Further, gates for both NMOS and PMOS devices are doped with n-type dopant and NMOS gates are self-aligned.

公开(公告)号：US5956611A

公开(公告)日：1999-09-21

申请号：US922871

申请日：1997-09-03

Applicant: David A. Cathey, Jr. ,  John K. Lee ,  Tianhong Zhang ,  Behnam Moradi

Inventor： David A. Cathey, Jr. ,  John K. Lee ,  Tianhong Zhang ,  Behnam Moradi

IPC: H01J1/05 ,  H01J9/02 ,  H01L21/00 ,  H01L21/4763 ,  H01L29/06

CPC classification number: H01J3/021 ,  H01J29/467 ,  H01J31/127 ,  H01J9/148 ,  H01J2203/0232 ,  H01J2329/463

Abstract: Semiconductor devices may be made by forming a silicided layer on a silicon material such as that used to form the extractor of a field emission display. The silicided layer may be self-aligned with the emitter of a field emission display. If the silicided layer is treated at a temperature above 1000.degree. C. by exposure to a nitrogen source, the silicide is resistant to subsequent chemical attack such as that involved in a buffered oxide etching process.

公开(公告)号：US5656886A

公开(公告)日：1997-08-12

申请号：US580613

申请日：1995-12-29

Applicant: Michael J. Westphal ,  Behnam Moradi

Inventor： Michael J. Westphal ,  Behnam Moradi

IPC: H01J9/02 ,  H01J9/12 ,  H01J1/46 ,  H01J1/62 ,  H01J21/10 ,  H01J63/04

CPC classification number: H01J9/025 ,  H01J2201/319

Abstract: Cold cathode passive matrix FEDs are fabricated by depositing a resistive layer on a substrate, and coated with a protective layer in which at least one hole is formed. Cathode material is deposited on the protective layer making direct contact with the resistive layer through the hole to form bases for the emitter tips which are subsequently etched from the cathode layer. The protective layer allows overetching of the cathode material to prevent tip-to-tip electrical shorts without attacking the underlying resistive layer.

Abstract translation: 冷阴极无源矩阵FED通过在衬底上沉积电阻层并涂覆有形成至少一个孔的保护层来制造。 阴极材料沉积在保护层上，通过孔与电阻层直接接触，形成发射极尖端的基底，随后从阴极层进行蚀刻。 保护层允许阴极材料的过蚀刻以防止尖端到尖端的电短路而不侵害下面的电阻层。

公开(公告)号：US08415223B2

公开(公告)日：2013-04-09

申请号：US13365472

申请日：2012-02-03

Applicant: Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

公开(公告)号：US08129781B2

公开(公告)日：2012-03-06

申请号：US12892691

申请日：2010-09-28

Applicant: Kirk D Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

Inventor： Kirk D Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US06930446B1

公开(公告)日：2005-08-16

申请号：US09386972

申请日：1999-08-31

Applicant: Behnam Moradi

Inventor： Behnam Moradi

IPC: H01J9/38

CPC classification number: H01J9/38

Abstract: A method is provided for manufacturing a field emission device, the method including operating the field emission device in a pressure of at most about 10−8 Torr for a selected period of time to evacuate outgassed materials and sealing the field emission device.

Abstract translation: 提供了一种用于制造场致发射器件的方法，该方法包括在至少约10 -8乇的压力下操作场致发射器件一段选定的时间，以排空除气材料并密封 场致发射装置。

公开(公告)号：US06831403B2

公开(公告)日：2004-12-14

申请号：US10327485

申请日：2002-12-20

Applicant: Behnam Moradi ,  Kanwal K. Raina ,  Michael J. Westphal

Inventor： Behnam Moradi ,  Kanwal K. Raina ,  Michael J. Westphal

IPC: H01J162

CPC classification number: H01J9/025 ,  H01J2329/00

Abstract: Improved field emission display includes a buffer layer of copper, aluminum, silicon nitride or doped or undoped amorphous, poly, or microcrystalline silicon located between a chromium gate electrode and associated dielectric layer in a cathode assembly. The buffer layer substantially reduces or eliminates the occurrence of an adverse chemical reaction between the chromium gate electrode and dielectric layer.

Abstract translation: 改进的场致发射显示器包括位于阴极组件中的铬栅电极和相关介电层之间的铜，铝，氮化硅或掺杂或未掺杂的非晶，多晶或微晶硅的缓冲层。 缓冲层基本上减少或消除了铬栅电极和电介质层之间不利的化学反应的发生。

公开(公告)号：US06562684B1

公开(公告)日：2003-05-13

申请号：US09651818

申请日：2000-08-30

Applicant: Behnam Moradi ,  Er-Xuan Ping ,  Lingyi A. Zheng ,  John Packard

Inventor： Behnam Moradi ,  Er-Xuan Ping ,  Lingyi A. Zheng ,  John Packard

IPC: H01L21336

CPC classification number: H01L21/02326 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/3144 ,  H01L28/40 ,  H01L28/84 ,  Y10S438/964

Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure. The structure includes a first capacitor electrode comprising a rugged polysilicon layer, a nitrogen-comprising layer on the rugged polysilicon layer, and a second capacitor electrode. The nitrogen-comprising layer is between the first and second capacitor electrodes.

Abstract translation: 本发明包括形成电介质材料的方法。 在坚固的多晶硅衬底的至少一些表面上形成含氮层以形成介电材料的第一部分。 在形成含氮层之后，至少一些基底用NO和N 2 O中的一种或两种进行干式氧化以形成介电材料的第二部分。 本发明还包括形成电容器的方法。 在衬底上形成一层坚固的硅，并且在坚固的硅层上形成含氮层。 一些粗糙的硅通过含氮层露出。 在形成含氮层之后，暴露的粗糙硅中的至少一些经受具有NO和N 2 O中的一种或两种的干燥氧化条件。 随后，在含氮层上形成导电材料层。 另外，本发明包括电容器结构。 该结构包括第一电容器电极，其包括坚固的多晶硅层，在凹凸多晶硅层上的含氮层和第二电容器电极。 含氮层位于第一和第二电容器电极之间。

公开(公告)号：US06361392B1

公开(公告)日：2002-03-26

申请号：US09860256

申请日：2001-05-18

Applicant: Behnam Moradi ,  Tianhong Zhang

Inventor： Behnam Moradi ,  Tianhong Zhang

IPC: H01J902

Abstract: A display apparatus includes a substrate and a plurality of emitters formed on the substrate. The apparatus also includes a dielectric layer formed on the substrate. The dielectric layer includes a plurality of openings each formed about one of the plurality of emitters. The dielectric layer and extraction grid together have a thickness, measured perpendicular to the substrate, similar to a height of the emitters above the substrate. The apparatus also includes an extraction grid formed on the dielectric layer. The extraction grid is formed substantially in a plane of tips of the plurality of emitters and includes openings each formed about and in close proximity to a tip of one of the plurality of emitters. The extraction grid includes germanium so that photons incident on exposed portions of the extraction grid are absorbed and are not transmitted to depletion regions associated with the emitters. This reduces distortion in operation of the display.

公开(公告)号：US06278229B1

公开(公告)日：2001-08-21

申请号：US09126494

申请日：1998-07-29

Applicant: Behnam Moradi ,  Tianhong Zhang

Inventor： Behnam Moradi ,  Tianhong Zhang

IPC: H01J102

CPC classification number: H01J3/022 ,  H01J31/127

Abstract: A display apparatus includes a substrate and a plurality of emitters formed on the substrate. The apparatus also includes a dielectric layer formed on the substrate. The dielectric layer includes a plurality of openings each formed about one of the plurality of emitters. The dielectric layer and extraction grid together have a thickness, measured perpendicular to the substrate, similar to a height of the emitters above the substrate. The apparatus also includes an extraction grid formed on the dielectric layer. The extraction grid is formed substantially in a plane of tips of the plurality of emitters and includes openings each formed about and in close proximity to a tip of one of the plurality of emitters. The extraction grid includes germanium so that photons incident on exposed portions of the extraction grid are absorbed and are not transmitted to depletion regions associated with the emitters. This reduces distortion in operation of the display.

Abstract translation: 显示装置包括基板和形成在基板上的多个发射体。 该装置还包括形成在基板上的电介质层。 电介质层包括多个开口，每个开口围绕多个发射器之一形成。 介电层和提取栅格一起具有垂直于衬底测量的厚度，类似于衬底上方的发射体的高度。 该装置还包括形成在电介质层上的提取栅格。 提取栅格基本上形成在多个发射器的尖端的平面中，并且包括各自形成在多个发射器中的一个的尖端附近并且紧邻其中一个的尖端的开口。 提取栅格包括锗，使得入射在提取栅格的暴露部分上的光子被吸收并且不传输到与发射器相关联的耗尽区域。 这减少了显示器的操作失真。