公开(公告)号：US5686843A

公开(公告)日：1997-11-11

申请号：US497126

申请日：1995-06-30

Applicant: Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

Inventor： Kenneth Edward Beilstein, Jr. ,  Claude Louis Bertin ,  Dennis Charles Dubois ,  Wayne John Howell ,  Gordon Arthur Kelley, Jr. ,  Christopher Paul Miller ,  David Jacob Perlman ,  Gustav Schrottke ,  Edmund Juris Sprogis ,  Jody John VanHorn

IPC: G01R31/26 ,  G01R1/04 ,  G01R31/28 ,  H01L21/66 ,  H01L25/00 ,  G01R31/02

CPC classification number: G01R31/2863 ,  G01R1/0483 ,  G01R31/2851 ,  G01R31/2886 ,  G01R31/2889 ,  H01L2924/0002

Abstract: Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.

Abstract translation: 阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。 通过将临时互连线连接到多芯片模块的访问表面来实现测试。 该临时互连布线使模块内的至少一些半导体器件芯片电互连。 在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。 如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。 此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。 描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

公开(公告)号：US20120132967A1

公开(公告)日：2012-05-31

申请号：US13364804

申请日：2012-02-02

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

IPC: H01L29/772 ,  H01L23/498 ,  H01L21/28

CPC classification number: H01L24/19 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract translation: 一种硅通孔结构和一种制造通硅通孔的方法。 该方法包括：（a）在硅衬底中形成沟槽，沟槽通向衬底的顶表面; （b）在所述沟槽的侧壁上形成二氧化硅层，所述二氧化硅层不填充所述沟槽; （c）用多晶硅填充沟槽中的剩余空间; （c）之后，（d）在衬底中制造至少一部分CMOS器件; （e）从所述沟槽去除所述多晶硅，所述电介质层残留在所述沟槽的侧壁上; （f）用导电芯重新填充沟槽; 在（f）之后，（g）在衬底的顶表面上形成一个或多个布线层，所述一个或多个布线层的布线层的布线层接触到所述导电芯的顶表面。

公开(公告)号：US08138036B2

公开(公告)日：2012-03-20

申请号：US12188228

申请日：2008-08-08

Applicant: Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

Inventor： Paul Stephen Andry ,  Edmund Juris Sprogis ,  Cornelia Kang-I Tsang

IPC: H01L21/8238 ,  H01L21/331 ,  H01L21/76

CPC classification number: H01L24/19 ,  H01L21/76898 ,  H01L21/823871 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/05552

Abstract: A through silicon via structure and a method of fabricating the through silicon via. The method includes: (a) forming a trench in a silicon substrate, the trench open to a top surface of the substrate; (b) forming a silicon dioxide layer on sidewalls of the trench, the silicon dioxide layer not filling the trench; (c) filling remaining space in the trench with polysilicon; after (c), (d) fabricating at least a portion of a CMOS device in the substrate; (e) removing the polysilicon from the trench, the dielectric layer remaining on the sidewalls of the trench; (f) re-filling the trench with an electrically conductive core; and after (f), (g) forming one or more wiring layers over the top surface of the substrate, a wire of a wiring level of the one or more wiring levels closet to the substrate contacting a top surface of the conductive core.

Abstract translation: 一种硅通孔结构和一种制造通硅通孔的方法。 该方法包括：（a）在硅衬底中形成沟槽，沟槽通向衬底的顶表面; （b）在所述沟槽的侧壁上形成二氧化硅层，所述二氧化硅层不填充所述沟槽; （c）用多晶硅填充沟槽中的剩余空间; （c）之后，（d）在衬底中制造至少一部分CMOS器件; （e）从所述沟槽去除所述多晶硅，所述电介质层残留在所述沟槽的侧壁上; （f）用导电芯重新填充沟槽; 在（f）之后，（g）在衬底的顶表面上形成一个或多个布线层，所述一个或多个布线层的布线层的布线层接触到所述导电芯的顶表面。

公开(公告)号：US08004289B2

公开(公告)日：2011-08-23

申请号：US12198221

申请日：2008-08-26

Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: G01R27/26 ,  G01R31/308

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US20110129996A1

公开(公告)日：2011-06-02

申请号：US13025678

申请日：2011-02-11

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L21/28

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US07851923B2

公开(公告)日：2010-12-14

申请号：US12410728

申请日：2009-03-25

Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

IPC: H01L23/48

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介电隔离的周边内对准并且延伸到所述电介质隔 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20090206488A1

公开(公告)日：2009-08-20

申请号：US12032642

申请日：2008-02-16

Applicant: Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

Inventor： Peter James Lindgren ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper ,  Kenneth Jay Stein

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和被环形导体层围绕的塞子层。 一种用于制造贯通衬底通孔的方法，包括在衬底内形成盲孔，并在盲孔内依次形成并随后在盲孔内进行平面化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：US07563714B2

公开(公告)日：2009-07-21

申请号：US11275542

申请日：2006-01-13

Applicant: Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

Inventor： Mete Erturk ,  Robert A. Groves ,  Jeffrey Bowman Johnson ,  Alvin Jose Joseph ,  Qizhi Liu ,  Edmund Juris Sprogis ,  Anthony Kendall Stamper

IPC: H01L21/44

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A backside contact structure and method of fabricating the structure. The method includes: forming a dielectric isolation in a substrate, the substrate having a frontside and an opposing backside; forming a first dielectric layer on the frontside of the substrate; forming a trench in the first dielectric layer, the trench aligned over and within a perimeter Of the dielectric isolation and extending to the dielectric isolation; extending the trench formed in the first dielectric layer through the dielectric isolation and into the substrate to a depth less than a thickness of the substrate; filling the trench and co-planarizing a top surface of the trench with a top surface of the first dielectric layer to form an electrically conductive through via; and thinning the substrate from a backside of the substrate to expose the through via.

Abstract translation: 背面接触结构及其制造方法。 该方法包括：在衬底中形成电介质隔离，所述衬底具有前侧和相对的背面; 在所述基板的前侧形成第一电介质层; 在所述第一电介质层中形成沟槽，所述沟槽在所述电介质隔离的周边内并且在所述介质隔离的周边内对准并且延伸到所述电介质隔离; 将形成在第一电介质层中的沟槽通过电介质隔离延伸到衬底中至小于衬底厚度的深度; 填充沟槽并将沟槽的顶表面与第一介电层的顶表面共平面化以形成导电通孔; 并从衬底的背面稀释衬底以露出通孔。

公开(公告)号：US20080308948A1

公开(公告)日：2008-12-18

申请号：US12198221

申请日：2008-08-26

Applicant: Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

Inventor： Thomas Joseph Dalton ,  Jeffrey Peter Gambino ,  Mark David Jaffe ,  Stephen Ellinwood Luce ,  Edmund Juris Sprogis

IPC: H01L23/52 ,  H01L21/66

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L25/50 ,  H01L2223/54453 ,  H01L2225/06513 ,  H01L2225/06531 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Structures for aligning wafers and methods for operating the same. The structure includes (a) a first semiconductor wafer including a first capacitive coupling structure, and (b) a second semiconductor wafer including a second capacitive coupling structure. The first and second semiconductor wafers are in direct physical contact with each other via a common surface. If the first and second semiconductor wafers are moved with respect to each other by a first displacement distance of 1 nm in a first direction while the first and second semiconductor wafers are in direct physical contact with each other via the common surface, then a change of at least 10−18 F in capacitance of a first capacitor comprising the first and second capacitive coupling structures results. The first direction is essentially parallel to the common surface.

Abstract translation: 用于对准晶片的结构及其操作方法。 该结构包括（a）包括第一电容耦合结构的第一半导体晶片和（b）包括第二电容耦合结构的第二半导体晶片。 第一和第二半导体晶片经由公共表面彼此直接物理接触。 如果第一和第二半导体晶片在第一方向上相对于彼此移动了1nm的第一位移距离，同时第一和第二半导体晶片经由公共表面彼此直接物理接触，则 包括第一和第二电容耦合结构的第一电容器的电容的至少10-18F的结果。 第一个方向基本上平行于共同的表面。

公开(公告)号：US20080261121A1

公开(公告)日：2008-10-23

申请号：US11738004

申请日：2007-04-20

Applicant: Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

Inventor： Jeffrey Peter Gambino ,  Robert Kenneth Leidy ,  Kirk David Peterson ,  Jed Hickory Rankin ,  Edmund Juris Sprogis

IPC: G03C5/00 ,  G03F1/00

CPC classification number: G03F1/30 ,  G03F1/48 ,  G03F1/54

Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.

Abstract translation: 光掩模和制造光掩模的方法。 所述光掩模包括：对所选择的波长或辐射波长透明的衬底，所述衬底具有顶表面和相对的底表面，所述衬底具有可打印区域和不可打印区域; 所述可印刷区域具有在所述基板的与所述透明区域相邻的顶表面上方的第一不透明区域，所述第一不透明区域的每个不透明区域具有侧壁和相对的顶表面和底表面，所述第一不透明区域包括金属; 所述不可打印区域包括在所述基板的顶表面上方升高的金属第二不透明区域，所述第二不透明区域具有侧壁和相对的顶部和底部表面，所述第二不透明区域包括所述金属; 以及在第一和第二不透明区域的顶表面和侧壁上的共形保护性金属氧化物覆盖层。 保形层通过氧化形成。