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    DSP reciever with high speed low BER ADC
    21.
    发明授权
    DSP reciever with high speed low BER ADC 有权
    具有高速低BER ADC的DSP接收器

    公开(公告)号：US08836553B2

    公开(公告)日：2014-09-16

    申请号：US13754374

    申请日：2013-01-30

    Applicant: Broadcom Corporation

    Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

    IPC: H03M1/10

    CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

    Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

    Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

    COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES
    22.
    发明申请
    COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES 有权
    针对高速串口的紧凑型低功耗全数字CMOS时钟发生器

    公开(公告)号：US20140241442A1

    公开(公告)日：2014-08-28

    申请号：US13946981

    申请日：2013-07-19

    Applicant: BROADCOM CORPORATION

    Inventor： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

    IPC: H03L7/00

    CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

    Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

    Abstract translation: 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。

    MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END
    23.
    发明申请
    MULTI-PROTOCOL COMMUNICATIONS RECEIVER WITH SHARED ANALOG FRONT-END 有权
    多协议通信采用共享模拟前端

    公开(公告)号：US20130243072A1

    公开(公告)日：2013-09-19

    申请号：US13871831

    申请日：2013-04-26

    Applicant: BROADCOM CORPORATION

    Inventor： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

    IPC: H04L27/00

    CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

    Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

    Abstract translation: 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。

    HIGH-SPEED, LOW-POWER RECONFIGURABLE VOLTAGE-MODE DAC-DRIVER
    24.
    发明申请
    HIGH-SPEED, LOW-POWER RECONFIGURABLE VOLTAGE-MODE DAC-DRIVER 有权
    高速，低功耗可重构电压模式DAC驱动器

    公开(公告)号：US20160182080A1

    公开(公告)日：2016-06-23

    申请号：US14616566

    申请日：2015-02-06

    Applicant: BROADCOM CORPORATION

    Inventor： Anand Jitendra Vasani ,  Ali Nazemi ,  Jun Cao ,  Afshin Momtaz

    IPC: H03M1/68 ,  H03M1/10 ,  H03M1/74 ,  H03M1/00

    CPC classification number: H03M1/68 ,  H03M1/002 ,  H03M1/068 ,  H03M1/1028 ,  H03M1/1047 ,  H03M1/74 ,  H03M1/80

    Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

    Abstract translation: 低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。 每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。 每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。 一个或多个相应阻抗的第二节点耦合到输出节点。

    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES
    26.
    发明申请
    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES 有权
    QUASI-DIGITAL接收器用于高速伺服系统

    公开(公告)号：US20140146922A1

    公开(公告)日：2014-05-29

    申请号：US13720623

    申请日：2012-12-19

    Applicant: BROADCOM CORPORATION

    Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

    IPC: H04L25/02

    CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

    Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

    Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

    TRANSCEIVER INCLUDING A HIGH LATENCY COMMUNICATION CHANNEL AND A LOW LATENCY COMMUNICATION CHANNEL
    27.
    发明申请
    TRANSCEIVER INCLUDING A HIGH LATENCY COMMUNICATION CHANNEL AND A LOW LATENCY COMMUNICATION CHANNEL 有权
    收发器包括高延迟通信信道和低延迟通信信道

    公开(公告)号：US20140126613A1

    公开(公告)日：2014-05-08

    申请号：US13671340

    申请日：2012-11-07

    Applicant: BROADCOM CORPORATION

    Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

    IPC: H03D3/02

    CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

    Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

    Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

    METHOD AND APPARATUS FOR PASSIVE EQUALIZATION AND SLEW-RATE CONTROL
    30.
    发明申请
    METHOD AND APPARATUS FOR PASSIVE EQUALIZATION AND SLEW-RATE CONTROL 有权
    无源均衡和频率控制的方法和装置

    公开(公告)号：US20150092829A1

    公开(公告)日：2015-04-02

    申请号：US14072641

    申请日：2013-11-05

    Applicant: Broadcom Corporation

    Inventor： Tamer ALI ,  Hassan Maarefi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz

    IPC: H04L25/03

    CPC classification number: H04L25/03019 ,  H04L25/0288 ,  H04L25/03885 ,  H04L2025/03471 ,  H04L2025/03681

    Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.

    Abstract translation: 用于信号的无源均衡和转换速率控制的装置包括第一分支，其包括与均衡电容器串联耦合的第一驱动器，以及包括与电阻器串联耦合的第二驱动器的第二分支。 第二分支可以与第一分支并联耦合，并且第一分支可以被配置为基于模式控制信号使能信号的无源均衡或转换速率控制之一。

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