公开(公告)号：US09087741B2

公开(公告)日：2015-07-21

申请号：US13179990

申请日：2011-07-11

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Balasubramanian S. Haran

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Balasubramanian S. Haran

IPC分类号： H01L27/12 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02592 ,  H01L21/0332 ,  H01L21/283 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/32053 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0922 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/167 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6656

摘要： An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.

摘要翻译： 一种用于产生具有用于NMOS和PMOS的双凸起源极和漏极的CMOS的装置和方法。 两个堆叠门上的间隔物的厚度相同。 在该方法中，在表面上形成第一绝缘层。 然后第一区域被掩蔽，而另一区域具有蚀刻掉的第一层，并且在该区域上生长外延源和漏极。 第二层形成于所有暴露的表面。 然后在第一区域被蚀刻掉的同时掩蔽第二区域。 外延源极和漏极形成在第一区域上。 第二区域也可以通过加入一薄层未掺杂的硅然后氧化来掩蔽。 掩盖第二个区域的另一种方法是使用硬面罩。 形成第二源和漏极的另一种方法是使用无定形材料。

公开(公告)号：US09059243B2

公开(公告)日：2015-06-16

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08664050B2

公开(公告)日：2014-03-04

申请号：US13424447

申请日：2012-03-20

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0653 ,  H01L21/76224 ,  H01L21/84 ,  H01L29/66545

摘要： A structure and method to improve ETSOI MOSFET devices. A wafer is provided including regions with at least a first semiconductor layer overlying an oxide layer overlying a second semiconductor layer. The regions are separated by a STI which extends at least partially into the second semiconductor layer and is partially filled with a dielectric. A gate structure is formed over the first semiconductor layer and during the wet cleans involved, the STI divot erodes until it is at a level below the oxide layer. Another dielectric layer is deposited over the device and a hole is etched to reach source and drain regions. The hole is not fully landed, extending at least partially into the STI, and an insulating material is deposited in said hole.

摘要翻译： 改进ETSOI MOSFET器件的结构和方法。 提供晶片，其包括具有覆盖在第二半导体层上的氧化物层的至少第一半导体层的区域。 这些区域由至少部分地延伸到第二半导体层中并且部分地填充有电介质的STI分开。 在第一半导体层上形成栅极结构，并且在涉及的湿清洗期间，STI纹路侵蚀直到其处于低于氧化物层的水平。 在器件上沉积另一个介电层，并蚀刻一个孔以到达源极和漏极区。 孔不完全落地，至少部分地延伸到STI中，并且绝缘材料沉积在所述孔中。

公开(公告)号：US20130295730A1

公开(公告)日：2013-11-07

申请号：US13487511

申请日：2012-06-04

申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

IPC分类号： H01L21/336

CPC分类号： H01L27/1203 ,  H01L21/84

摘要： A method of creating a semiconductor integrated circuit is disclosed. The method includes forming a first field effect transistor (FET) device and a second FET device on a semiconductor substrate. The method includes epitaxially growing raised source/drain (RSD) structures for the first FET device at a first height. The method includes epitaxially growing raised source/drain (RSD) structures for the second FET device at a second height. The second height is greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

摘要翻译： 公开了一种制造半导体集成电路的方法。 该方法包括在半导体衬底上形成第一场效应晶体管（FET）器件和第二FET器件。 该方法包括在第一高度上外延生长用于第一FET器件的升高的源极/漏极（RSD）结构。 该方法包括在第二高度上外延生长用于第二FET器件的升高的源极/漏极（RSD）结构。 第二高度大于第一高度，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

公开(公告)号：US08372705B2

公开(公告)日：2013-02-12

申请号：US13013801

申请日：2011-01-25

申请人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

发明人： Lahir Shaik Adam ,  Sanjay C Mehta ,  Balasubramanian S Haran ,  Bruce B. Doris

IPC分类号： H01L21/8238

CPC分类号： H01L29/78 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/092 ,  H01L29/4983 ,  H01L29/7843

摘要： CMOS transistors are formed incorporating a gate electrode having tensely stressed spacers on the gate sidewalls of an n channel field effect transistor and having compressively stressed spacers on the gate sidewalls of a p channel field effect transistor to provide differentially stressed channels in respective transistors to increase carrier mobility in the respective channels.

摘要翻译： 形成CMOS晶体管，其结合有在n沟道场效应晶体管的栅极侧壁上具有紧张应力间隔物的栅极，并且在ap沟道场效应晶体管的栅极侧壁上具有压缩应力间隔物，以在相应晶体管中提供差分应力通道以增加载流子迁移率 在各自的频道。

公开(公告)号：US20120292705A1

公开(公告)日：2012-11-22

申请号：US13108290

申请日：2011-05-16

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Ghavam G. Shahidi

IPC分类号： H01L27/092

CPC分类号： H01L27/1203 ,  H01L21/823864 ,  H01L21/823892

摘要： A semiconductor structure which includes a semiconductor on insulator (SOI) substrate. The SOI substrate includes a base semiconductor layer; a buried oxide (BOX) layer in contact with the base semiconductor layer; and an SOI layer in contact with the BOX layer. The semiconductor structure further includes a circuit formed with respect to the SOI layer, the circuit including an N type field effect transistor (NFET) having source and drain extensions in the SOI layer and a gate; and a P type field effect transistor (PFET) having source and drain extensions in the SOI layer and a gate. There may also be a well under each of the NFET and PFET. There is a nonzero electrical bias being applied to the. SOI substrate. One of the NFET extensions and PFET extensions may be underlapped with respect to the NFET gate or PFET gate, respectively.

摘要翻译： 一种半导体结构，其包括绝缘体上半导体（SOI）基板。 SOI衬底包括基极半导体层; 与基底半导体层接触的掩埋氧化物（BOX）层; 以及与BOX层接触的SOI层。 半导体结构还包括相对于SOI层形成的电路，该电路包括在SOI层中具有源极和漏极延伸的N型场效应晶体管（NFET）和栅极; 以及在SOI层中具有源极和漏极延伸的P型场效应晶体管（PFET）和栅极。 每个NFET和PFET下面也可以有一个阱。 有一个非零的电偏压被施加到。 SOI衬底。 NFET扩展和PFET扩展中的一个可能分别相对于NFET栅极或PFET栅极被覆盖。

公开(公告)号：US20120280290A1

公开(公告)日：2012-11-08

申请号：US13102073

申请日：2011-05-06

申请人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

发明人： Ali Khakifirooz ,  Kangguo Cheng ,  Bruce B. Doris ,  Wilfried E. Haensch ,  Balasubramanian S. Haran ,  Pranita Kulkarni

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/0207 ,  H01L21/28518 ,  H01L21/76802 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L27/1104 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7834

摘要： A common cut mask is employed to define a gate pattern and a local interconnect pattern so that local interconnect structures and gate structures are formed with zero overlay variation relative to one another. A local interconnect structure may be laterally spaced from a gate structure in a first horizontal direction, and contact another gate structure in a second horizontal direction that is different from the first horizontal direction. Further, a gate structure may be formed to be collinear with a local interconnect structure that adjoins the gate structure. The local interconnect structures and the gate structures are formed by a common damascene processing step so that the top surfaces of the gate structures and the local interconnect structures are coplanar with each other.

摘要翻译： 采用公共切割掩模来限定栅极图案和局部互连图案，使得局部互连结构和栅极结构相对于彼此形成为零覆盖变化。 局部互连结构可以在第一水平方向上与栅极结构横向间隔开，并且在与第一水平方向不同的第二水平方向上接触另一个栅极结构。 此外，栅极结构可以形成为与邻接栅极结构的局部互连结构共线。 局部互连结构和栅极结构通过公共镶嵌处理步骤形成，使得栅极结构的顶表面和局部互连结构彼此共面。

公开(公告)号：US20140001555A1

公开(公告)日：2014-01-02

申请号：US13537141

申请日：2012-06-29

申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

公开(公告)号：US20130344677A1

公开(公告)日：2013-12-26

申请号：US13531780

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

公开(公告)号：US20130341754A1

公开(公告)日：2013-12-26

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L29/06

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.