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    High-voltage LDMOSFET and applications therefor in standard CMOS
    21.
    发明授权
    High-voltage LDMOSFET and applications therefor in standard CMOS 有权
    高压LDMOSFET及其在标准CMOS中的应用

    公开(公告)号：US08264039B2

    公开(公告)日：2012-09-11

    申请号：US10952708

    申请日：2004-09-28

    Applicant: Bin Wang ,  William T. Colleran ,  Chih-Hsin Wang

    Inventor： Bin Wang ,  William T. Colleran ,  Chih-Hsin Wang

    IPC: H01L29/78

    CPC classification number: H01L29/4983 ,  H01L29/0653 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/7835

    Abstract: A high-voltage LDMOSFET includes a semiconductor substrate, in which a gate well is formed. A source well and a drain well are formed on either side of the gate well, and include insulating regions within them that do not reach the full depth. An insulating layer is disposed on the substrate, covering the gate well and a portion of the source well and the drain well. A conductive gate is disposed on the insulating layer. Biasing wells are formed adjacent the source well and the drain well. A deep well is formed in the substrate such that it communicates with the biasing wells and the gate well, while extending under the source well and the drain well, such as to avoid them. Biasing contacts at the top of the biasing wells bias the deep well, and therefore also the gate well.

    Abstract translation: 高压LDMOSFET包括其中形成栅极阱的半导体衬底。 源极阱和漏极阱形成在栅极阱的任一侧上，并且在其内部包括未达到全部深度的绝缘区域。 绝缘层设置在衬底上，覆盖栅极阱以及源极阱和漏极阱的一部分。 导电栅极设置在绝缘层上。 在源阱和排水井附近形成偏置井。 在衬底中形成深阱，使得其在偏压井和浇口井下连通，同时在源井和排水井下方延伸，以避免它们。 偏置井顶部的偏置接触偏压深井，因此井也很好。

    Isolation for non-volatile memory cell array
    23.
    发明授权
    Isolation for non-volatile memory cell array 有权
    隔离非易失性存储单元阵列

    公开(公告)号：US08072023B1

    公开(公告)日：2011-12-06

    申请号：US12262599

    申请日：2008-10-31

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/788

    CPC classification number: H01L27/11568

    Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.

    Abstract translation: 一种存储装置，包括以存储区域间隔排列的多个存储区域。 多个导线与存储区间隔并列。 提供一个或多个隔离，每个隔离邻近一个或多个导体线并且并置一个或多个作为虚拟存储区域的存储区域。 存储区域是存储单元中的电荷存储区域，并且每个存储单元进一步包括第一单元区域，第二单元区域和单元通道并置电荷存储区域并位于第一单元区域和第二单元区域之间。 第一阵列区域和第二阵列区域被隔离物中的第一个隔离; 每个阵列区域包括一个或多个存储单元组，其中每个存储器单元包括存储区域之一。

    Non-volatile memory cell array and logic
    24.
    发明授权
    Non-volatile memory cell array and logic 有权
    非易失性存储单元阵列和逻辑

    公开(公告)号：US07847374B1

    公开(公告)日：2010-12-07

    申请号：US12168448

    申请日：2008-07-07

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/73

    CPC classification number: H01L27/24 ,  H01L27/1026

    Abstract: A semiconductor device comprising a memory region including one or more transistor string arrays, a logic region including one or more logic transistors and an isolation region for isolating the logic transistors. The string array includes a plurality, T, of bipolar junction transistors. The string array includes a common collector region for the T bipolar junction transistors, a common base region for the T bipolar junction transistors, a plurality of emitters, one emitter for each of the T bipolar junction transistors, a number, B, of base contacts for the T bipolar junction transistors where the base contacts electrically couple the common base region and where the number of base contacts, B, is less than the number of transistors, T.

    Abstract translation: 一种半导体器件，包括包括一个或多个晶体管串阵列的存储区域，包括一个或多个逻辑晶体管的逻辑区域和用于隔离逻辑晶体管的隔离区域。 串阵列包括多个T型双极结型晶体管。 串阵列包括用于T双极结晶体管的公共集电极区域，用于T双极结晶体管的公共基极区域，多个发射极，每个T双极结晶体管的一个发射极，基极触点的数量B 对于其中基极接触电耦合公共基极区域并且其中基极触点数B小于晶体管数量T的T双极结晶体管。

    Electrically alterable memory cell
    26.
    发明授权
    Electrically alterable memory cell 有权
    电可变存储单元

    公开(公告)号：US07759719B2

    公开(公告)日：2010-07-20

    申请号：US11120691

    申请日：2005-05-02

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/786

    CPC classification number: H01L29/42324 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A nonvolatile memory cell is provided. The cell has a charge filter, a tunneling gate, a ballistic gate, a charge storage layer, a source, and a drain with a channel defined between the source and drain. The charge filter permits transporting of charge carriers of one polarity type from the tunneling gate through the blocking material and the ballistic gate to the charge storage layer while blocking the transport of charge carriers of an opposite polarity from the ballistic gate to the tunneling gate. Further embodiments of the present invention provide a cell having a charge filter, a supplier gate, a tunneling gate, a ballistic gate, a source, a drain, a channel, and a charge storage layer. The present invention further provides an energy band engineering method permitting the memory cell be operated without suffering from disturbs, from dielectric breakdown, from impact ionization, and from undesirable RC effects.

    Abstract translation: 提供非易失性存储单元。 电池具有在源极和漏极之间限定的沟道的电荷滤波器，隧道栅极，弹道栅极，电荷存储层，源极和漏极。 电荷滤波器允许将一种极性类型的载流子从隧道栅极通过阻挡材料和弹道栅传输到电荷存储层，同时阻止相反极性的电荷载体从弹道栅极传输到隧道栅极。 本发明的另外的实施例提供了一种具有电荷滤波器，供电门，隧道门，弹道门，源极，漏极，沟道和电荷存储层的电池。 本发明进一步提供了允许存储器单元在不受到电介质击穿，不受冲击电离和不期望的RC影响的干扰的情况下运行的能带工程方法。

    Method and apparatus transporting charges in semiconductor device and semiconductor memory device
    30.
    发明申请
    Method and apparatus transporting charges in semiconductor device and semiconductor memory device 有权
    在半导体器件和半导体存储器件中传输电荷的方法和装置

    公开(公告)号：US20070281425A1

    公开(公告)日：2007-12-06

    申请号：US11879090

    申请日：2007-07-16

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  G11C16/0416 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/7885 ,  H01L29/792

    Abstract: A method of providing a memory cell comprises providing a semiconductor substrate including a body of a first conductivity type, first and second regions of a second conductivity type and a channel between the first and second regions; arranging a first insulator layer adjacent to the channel; arranging a charge storage region adjacent to the first insulator layer; arranging a second insulator layer adjacent to the charge storage region; arranging a first conductive region adjacent to the second insulator layer; arranging a filter adjacent to the first conductive region; and arranging a second conductive region adjacent to the filter. The second conductive region overlaps the first conductive region at an overlap surface. A line perpendicular to the overlap surface intersects at least a portion of the charge storage region.

    Abstract translation: 提供存储单元的方法包括：提供包括第一导电类型的主体，第二导​​电类型的第一和第二区域以及第一和第二区域之间的通道的半导体衬底; 布置与所述通道相邻的第一绝缘体层; 配置与所述第一绝缘体层相邻的电荷存储区域; 布置与电荷存储区域相邻的第二绝缘体层; 布置与所述第二绝缘体层相邻的第一导电区域; 布置与所述第一导电区域相邻的过滤器; 以及布置与所述过滤器相邻的第二导电区域。 第二导电区域在重叠表面处与第一导电区域重叠。 垂直于重叠表面的线与电荷存储区域的至少一部分相交。

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