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38 条记录 (耗时 0.034 秒)

    Micro-mirror package
    21.
    发明授权
    Micro-mirror package 有权
    微镜包装

    公开(公告)号：US07053488B2

    公开(公告)日：2006-05-30

    申请号：US10905400

    申请日：2004-12-31

    申请人： Kuo-Chung Yee

    发明人： Kuo-Chung Yee

    IPC分类号： H01L29/40

    CPC分类号： G02B26/0816 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/00014

    摘要： A micro-mirror package comprising a substrate, a bottom substrate, a cover substrate, a semiconductor chip, a first adhesive, a second adhesive, a plurality of wires and a lid is provided. The substrate has a circular wall. The bottom substrate is disposed on the substrate within the circular wall. The first adhesive is provided with first spacers for attaching the cover substrate to the semiconductor chip and setting the cover substrate and the semiconductor chip apart. The second adhesive is provided with second spacers for attaching the semiconductor chip to the bottom substrate and setting the semiconductor chip and the bottom substrate apart. The wires are used for electrically connecting the semiconductor chip and the substrate. The lid is disposed on top of the circular wall.

    摘要翻译： 提供了包括基板，底部基板，盖基板，半导体芯片，第一粘合剂，第二粘合剂，多根电线和盖子的微反射镜封装。 基板具有圆形壁。 底部基板设置在圆形壁内的基板上。 第一粘合剂设置有用于将盖基板附接到半导体芯片并将盖基板和半导体芯片分开的第一间隔件。 第二粘合剂设置有用于将半导体芯片附接到底部基板并将半导体芯片和底部基板分开的第二间隔件。 电线用于电连接半导体芯片和基板。 盖子设置在圆形壁的顶部。

    Method of making a package structure by dicing a wafer from the backside surface thereof
    22.
    发明授权
    Method of making a package structure by dicing a wafer from the backside surface thereof 有权
    通过从其背面切割晶片来制造封装结构的方法

    公开(公告)号：US07033914B2

    公开(公告)日：2006-04-25

    申请号：US10919178

    申请日：2004-08-16

    申请人： Kuo-Chung Yee

    发明人： Kuo-Chung Yee

    IPC分类号： H01L21/301

    CPC分类号： B81C1/00333 ,  H01L21/67092 ,  H01L21/78

    摘要： The present invention relates to a method of making a package structure by dicing a wafer from the backside surface thereof comprising: (a) providing a first wafer having a active surface, a backside surface and a plurality of scribe lines defining a plurality of chips, wherein each chip has an annular body thereon; (b) dicing the first wafer from the active surface to form a reference coordinate; (c) providing a second wafer; (d) covering and joining the second wafer to the first wafer to form a plurality of cavities; and (e) dicing the corresponding positions of the scribe lines of the first wafer from the backside surface thereof according to the predetermined distance from the reference coordinate so as to form an individual package structure. As a result, the manufacture time is reduced.

    摘要翻译： 本发明涉及通过从其背面切割晶片来制造封装结构的方法，包括：（a）提供具有有源表面的第一晶片，背面和限定多个芯片的多个划线， 其中每个芯片在其上具有环形体; （b）从活性表面切割第一晶片以形成参考坐标; （c）提供第二晶片; （d）将第二晶片覆盖并接合到第一晶片以形成多个空腔; 并且（e）根据与参考坐标的预定距离，从其背面切割第一晶片的划线的对应位置，以形成单独的封装结构。 结果，制造时间缩短。

    Three-dimensional package and method of making the same
    25.
    发明授权
    Three-dimensional package and method of making the same 有权
    三维包装及其制作方法

    公开(公告)号：US07642132B2

    公开(公告)日：2010-01-05

    申请号：US11584546

    申请日：2006-10-23

    申请人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    发明人： Min-Lung Huang ,  Wei-Chung Wang ,  Po-Jen Cheng ,  Kuo-Chung Yee ,  Ching-Huei Su ,  Jian-Wen Lo ,  Chian-Chi Lin

    IPC分类号： H01L21/44

    CPC分类号： H01L25/0657 ,  H01L21/76898 ,  H01L25/50 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05024 ,  H01L2224/05548 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2224/05099

    摘要： The present invention relates to a three-dimensional package and a method of making the same. The method comprises: (a) providing a semiconductor body; (b) forming at least one blind hole in the semiconductor body; (c) forming an isolation layer on the side wall of the blind hole; (d) forming a conductive layer on the isolation layer; (e) patterning the conductive layer; (f) removing a part of the lower surface of the semiconductor body and a part of the isolation layer, so as to expose a part of the conductive layer; (g) forming a solder on the lower end of the conductive layer; (h) stacking a plurality of the semiconductor bodies, and performing a reflow process; and (i) cutting the stacked semiconductor bodies, so as to form a plurality of three-dimensional packages. As such, the lower end of the conductive layer and the solder thereon are “inserted” into the space formed by the conductive layer of the lower semiconductor body, so as to enhance the joining between the conductive layer and the solder, and effectively reduce the overall height of the three-dimensional packages after joining.

    摘要翻译： 本发明涉及三维包装及其制造方法。 该方法包括：（a）提供半导体本体; （b）在半导体本体中形成至少一个盲孔; （c）在盲孔的侧壁上形成隔离层; （d）在隔离层上形成导电层; （e）图案化导电层; （f）去除所述半导体主体的下表面的一部分和所述隔离层的一部分，以暴露所述导电层的一部分; （g）在导电层的下端形成焊料; （h）堆叠多个半导体体，进行回流处理; 和（i）切割堆叠的半导体本体，以便形成多个三维封装。 因此，导电层的下端和其上的焊料被“插入”到由下半导体本体的导电层形成的空间中，以便增强导电层和焊料之间的接合，并且有效地减少 加入后三维包装的整体高度。

    Mold and method of molding semiconductor devices
    27.
    发明授权
    Mold and method of molding semiconductor devices 有权
    模具和模制半导体器件的方法

    公开(公告)号：US07247267B2

    公开(公告)日：2007-07-24

    申请号：US10710906

    申请日：2004-08-12

    申请人： Jen-Chieh Kao ,  Kuo-Chung Yee

    发明人： Jen-Chieh Kao ,  Kuo-Chung Yee

    IPC分类号： B29C70/72 ,  H01L21/56

    CPC分类号： B29C45/0025 ,  B29C45/14639 ,  H01L21/565 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A mold for molding semiconductor devices mounted on a package substrate is provided. The mold comprises a top mold and a bottom mold. The top mold has a top runner, at least a first dummy runner and a plurality of mold cavities. The first dummy runner connects with the top runner and the top runner extends into a space between the mold cavities. The mold cavities for accommodating the semiconductor devices are connected to the top runner. The bottom mold has a bottom runner and at least a second dummy runner. The second dummy runner connects with the bottom runner. The second dummy runner is above but separated from the first dummy runner by the package substrate.

    摘要翻译： 提供了一种用于模制安装在封装衬底上的半导体器件的模具。 模具包括顶模和底模。 顶部模具具有顶部流道，至少第一模拟流道和多个模具腔。 第一个虚拟跑步者与顶级跑步者相连，顶级赛跑者延伸到模具腔之间的空间。 用于容纳半导体器件的模腔连接到顶部流道。 底模具有底流道和至少第二模拟流道。 第二个虚拟跑步者与底下的跑步者相连。 第二虚拟跑步者位于上方，但是通过封装衬底与第一虚拟跑步者分离。

    Method of making a package structure by dicing a wafer from the backside surface thereof
    28.
    发明申请
    Method of making a package structure by dicing a wafer from the backside surface thereof 有权
    通过从其背面切割晶片来制造封装结构的方法

    公开(公告)号：US20050042844A1

    公开(公告)日：2005-02-24

    申请号：US10919178

    申请日：2004-08-16

    申请人： Kuo-Chung Yee

    发明人： Kuo-Chung Yee

    IPC分类号： H01L21/00 ,  H01L21/78

    CPC分类号： B81C1/00333 ,  H01L21/67092 ,  H01L21/78

    摘要： The present invention relates to a method of making a package structure by dicing a wafer from the backside surface thereof comprising: (a) providing a first wafer having a active surface, a backside surface and a plurality of scribe lines defining a plurality of chips, wherein each chip has an annular body thereon; (b) dicing the first wafer from the active surface to form a reference coordinate; (c) providing a second wafer; (d) covering and joining the second wafer to the first wafer to form a plurality of cavities; and (e) dicing the corresponding positions of the scribe lines of the first wafer from the backside surface thereof according to the predetermined distance from the reference coordinate so as to form an individual package structure. As a result, the manufacture time is reduced.

    摘要翻译： 本发明涉及通过从其背面切割晶片来制造封装结构的方法，包括：（a）提供具有有源表面的第一晶片，背面和限定多个芯片的多个划线， 其中每个芯片在其上具有环形体; （b）从活性表面切割第一晶片以形成参考坐标; （c）提供第二晶片; （d）将第二晶片覆盖并接合到第一晶片以形成多个空腔; 并且（e）根据与参考坐标的预定距离，从其背面切割第一晶片的划线的对应位置，以形成单独的封装结构。 结果，制造时间缩短。