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    Optical integrated circuit element package and process for making the same
    1.
    发明授权
    Optical integrated circuit element package and process for making the same 有权
    光集成电路元件封装及其制造方法

    公开(公告)号：US06693364B2

    公开(公告)日：2004-02-17

    申请号：US10355152

    申请日：2003-01-31

    申请人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

    发明人： Su Tao ,  Kuo Chung Yee ,  Jen Chieh Kao ,  Chih Lung Chen ,  Hsing Jung Liau

    IPC分类号： H01L2348

    CPC分类号： H01L31/0203 ,  H01L21/563 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2224/05599

    摘要： An optical integrated circuit element package comprises a substrate, an upper chip, a lower chip, an optical-transparent underfill, and a sealing compound. The substrate has a plurality of solder balls disposed on a surface of the substrate, a plurality of bonding pads electrically connected to the solder balls, a cover attached to the other surface of the substrate, and a cavity to expose the cover. The upper chip is provided with a plurality of bumps and is adhered to the exposed cover in the cavity by a thermal gap fill. The lower chip has a plurality of bonding pads electrically connected to the plurality of bumps of the upper chip and has a plurality of bumps electrically connected to the plurality of bonding pads of the substrate. The optical-transparent underfill is disposed between the lower chip and the upper chip. The sealing compound hermetically seals the space between the lower chip and the substrate.

    摘要翻译： 一种光学集成电路元件封装，包括衬底，上部芯片，下部芯片，光学透明底部填充物和密封化合物。 衬底具有设置在衬底的表面上的多个焊球，与焊球电连接的多个接合焊盘，附接到衬底的另一个表面的盖以及露出罩的空腔。 上芯片设置有多个凸块，并且通过热间隙填充而粘附到空腔中的暴露盖。 下部芯片具有电连接到上部芯片的多个凸起的多个焊盘，并且具有电连接到该衬底的多个焊盘的多个凸块。 光学透明底部填充物设置在下部芯片和上部芯片之间。 密封组合物密封下部芯片和基板之间的空间。

    Microsystem package structure
    2.
    发明授权
    Microsystem package structure 有权
    微系统封装结构

    公开(公告)号：US06809852B2

    公开(公告)日：2004-10-26

    申请号：US10603957

    申请日：2003-06-24

    申请人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao ,  Chih-Lung Chen ,  Hsing-Jung Liau

    发明人： Su Tao ,  Kuo-Chung Yee ,  Jen-Chieh Kao ,  Chih-Lung Chen ,  Hsing-Jung Liau

    IPC分类号： G02B2600

    CPC分类号： G02B7/1821 ,  H01L2224/16145 ,  H01L2224/32225 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/0401

    摘要： The present invention relates to a package structure for a microsystem, comprising a substrate, a chip, an adhesive structure, a carrying substrate, a micro-mechanism, a plurality of wires, an annular body and a transparent plate. The chip is placed on the substrate. The annular adhesive structure having an opening is placed on the chip. The carrying substrate is placed on the adhesive structure, thus forming an interspace between the chip, the adhesive structure and the carrying substrate. The pressure inside the interspace can be balanced with the pressure outside the interspace through the opening. The micro-mechanism is disposed on the carrying substrate. The annular body is formed on the substrate and the transparent plate is attached on the annular body, thus forming a closed chamber between the substrate, the annular body and the transparent plate. The chip, the micro-mechanism, the adhesive structure, the carrying substrate and the wires are disposed within the closed chamber.

    摘要翻译： 本发明涉及一种用于微系统的封装结构，其包括基板，芯片，粘合结构，承载基板，微机构，多根导线，环形体和透明板。 将芯片放置在基板上。 具有开口的环形粘合剂结构被放置在芯片上。 携带衬底被放置在粘合剂结构上，从而在芯片，粘合剂结构和承载衬底之间形成间隙。 间隙内的压力可以通过开口与间隙外的压力平衡。 微机构设置在承载基板上。 环状体形成在基板上，透明板安装在环状体上，由此在基板，环状体和透明板之间形成封闭室。 芯片，微机构，粘合剂结构，承载基板和电线设置在封闭室内。

    Semiconductor chip package
    7.
    发明授权
    Semiconductor chip package 有权
    半导体芯片封装

    公开(公告)号：US07605020B2

    公开(公告)日：2009-10-20

    申请号：US11612393

    申请日：2006-12-18

    申请人： Su Tao ,  Shih Chang Lee

    发明人： Su Tao ,  Shih Chang Lee

    IPC分类号： H01L21/00

    CPC分类号： H01L23/36 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/49838 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/05599

    摘要： A method of manufacturing a semiconductor chip package includes mechanically and electrically connecting a semiconductor chip to a top surface of a main substrate, securely attaching the semiconductor chip to a recessed cavity on a bottom surface of an interconnection substrate, mechanically and electrically connecting the main substrate to the interconnection substrate, and cutting the main substrate to form a central substrate and a peripheral substrate wherein the semiconductor chip is disposed on the central substrate. The cutting step is conducted either (i) by forming a plurality of slots such that the central substrate and the peripheral substrate are partially conned to each other or (ii) by completely separating the central substrate and the peripheral substrate.

    摘要翻译： 制造半导体芯片封装的方法包括将半导体芯片机械地和电连接到主基板的顶表面，将半导体芯片牢固地连接到互连基板的底表面上的凹腔中，机械地和电连接主基板 并且切割主基板以形成中心基板和外围基板，其中半导体芯片设置在中心基板上。 切割步骤（i）通过形成多个狭缝进行，使得中心基板和外围基板彼此部分连接，或者（ii）通过完全分离中心基板和外围基板。

    Leadless semiconductor package
    8.
    发明授权
    Leadless semiconductor package 有权
    无铅半导体封装

    公开(公告)号：US07102241B2

    公开(公告)日：2006-09-05

    申请号：US10929503

    申请日：2004-08-31

    申请人： Su Tao

    发明人： Su Tao

    IPC分类号： H01L23/29 ,  H01L23/48

    CPC分类号： H01L23/492 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49811 ,  H01L24/48 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    摘要： A leadless semiconductor package disposed on a substrate includes a chip, a plurality of leads, wherein each lead has a metal layer and a first molding compound formed on the metal layer, a second molding compound disposed on the first molding compound, and a chip paddle for carrying the chip. The leads are connected to the chip by wire bonding technique. The metal layer is exposed out of the first molding compound; and the second molding compound encapsulates the chip with the chip paddle exposed out of the second molding compound.

    摘要翻译： 设置在基板上的无引线半导体封装包括芯片，多个引线，其中每个引线具有金属层和形成在金属层上的第一模塑料，设置在第一模塑料上的第二模塑料和芯片桨 用于携带芯片。 引线通过引线接合技术连接到芯片。 金属层露出第一模塑料; 并且所述第二模塑料封装所述芯片，所述芯片焊盘暴露于所述第二模塑料之外。

    Wafer level package structure with a heat slug
    10.
    发明授权
    Wafer level package structure with a heat slug 有权
    具有散热片的晶圆级封装结构

    公开(公告)号：US06946729B2

    公开(公告)日：2005-09-20

    申请号：US10417693

    申请日：2003-04-17

    申请人： Chun-Chi Lee ,  Su Tao

    发明人： Chun-Chi Lee ,  Su Tao

    IPC分类号： H01L23/31 ,  H01L23/433 ,  H01L23/34 ,  H01L23/02 ,  H01L23/48 ,  H01L23/495 ,  H05K7/20

    CPC分类号： H01L24/49 ,  H01L23/3128 ,  H01L23/4334 ,  H01L24/48 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

    摘要： A wafer level package structure and a method for packaging said wafer level package structure are described. The wafer level package structure at least comprises a die, a heat slug covering said die, a carrier for supporting said heat slug and said die, a plurality of wires electrically connecting said die and said carrier, and a mould compound encapsulating said die, said carrier, said heat slug and said wires. The method comprises the steps of: (a)providing a heat slug metal with a plurality of openings; (b)mounting said heat slug metal onto a wafer to dispose said openings on corresponding bonding pads of the wafer so as to expose said bonding pads; (c)sawing said combined heat slug metal and wafer into a plurality of die units; (d)attaching said die unit onto a carrier; (e)electrically connecting a plurality of wires to said die unit and said carrier; (f)encapsulating said wired die unit and said carrier. In the present invention, the heat slug metal and wafer can be sawed into a plurality of die units at the same time to improve the defect of the complicated process of individually sawing heat slug metal and wafer and individually combining heat slug metal and wafer in the conventional method.

    摘要翻译： 描述了晶片级封装结构和用于封装晶片级封装结构的方法。 晶片级封装结构至少包括一个管芯，一个覆盖所述管芯的散热片，一个用于支撑所述加热块和所述管芯的载体，多个电连接所述管芯和所述载体的电线以及封装所述管芯的模具化合物， 载体，所述热塞和所述电线。 该方法包括以下步骤：（a）提供具有多个开口的热块金属; （b）将所述加热块金属安装在晶片上以将所述开口布置在所述晶片的对应的焊盘上，以暴露所述焊盘; （c）将所述组合的热块金属和晶片锯切成多个模具单元; （d）将所述模具单元附接到载体上; （e）将多根电线电连接到所述模具单元和所述载体上; （f）封装所述有线芯片单元和所述载体。 在本发明中，可以同时将散热块金属和晶片锯成多个模具单元，以改善单独锯切热芯金属和晶片的复杂工艺的缺陷，并且将热块金属和晶片分别组合在 常规方法。