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55 条记录 (耗时 0.047 秒)

    Semiconductor chip using both polysilicon and metal gate devices
    23.
    发明授权
    Semiconductor chip using both polysilicon and metal gate devices 有权

    公开(公告)号：US06777761B2

    公开(公告)日：2004-08-17

    申请号：US10214084

    申请日：2002-08-06

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Kwong Hon Wong

    IPC分类号： H01L2976

    CPC分类号： H01L21/823842

    摘要： A semiconductor structure (and method for forming) having transistors having both metal gates and polysilicon gates on a single substrate in a single process is disclosed. The method forms a gate dielectric layer on the substrate and forms the metal seed layer on the gate oxide layer. The method patterns the metal seed layer to leave metal seed material in metal gate seed areas above the substrate. Next, the method patterns a polysilicon layer into polysilicon structures above the substrate. Some of the polysilicon structures comprise sacrificial polysilicon structures on the metal gate seed areas and the remaining ones of the polysilicon structures comprise the polysilicon gates. The patterning of the polysilicon gates forms the sacrificial gates above all the metal gate seed areas. Following that, the invention forms sidewall spacers, and source and drain regions adjacent the polysilicon structures. Then, the invention protects the polysilicon gates, removes the sacrificial polysilicon structures, and plates the metal gate seed areas to form the metal gates. The sidewall spacers self-align the metal gates. The plating process forms the metal gates of pure metal. All thermal processing that raises the temperature above a damage threshold for the metal is performed before the plating process.

    Three-dimensional island pixel photo-sensor
    24.
    发明授权
    Three-dimensional island pixel photo-sensor 有权
    三维岛像素光电传感器

    公开(公告)号：US06720595B2

    公开(公告)日：2004-04-13

    申请号：US09922077

    申请日：2001-08-06

    申请人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    发明人： Lawrence A. Clevenger ,  Louis L. Hsu ,  Carl J. Radens ,  Li-Kong Wang ,  Kwong Hon Wong

    IPC分类号： H01L31062

    CPC分类号： H01L27/14634 ,  H01L27/1463 ,  H01L27/14643

    摘要： A method and structure for a photodiode array comprising a plurality of photodiode cores, light sensing sidewalls along an exterior of the cores, logic circuitry above the cores, trenches separating the cores, and a transparent material in the trenches is disclosed. With the invention, the sidewalls are perpendicular to the surface of the photodiode that receives incident light. The light sensing sidewalls comprise a junction region that causes electron transfer when struck with light. The sidewalls comprise four vertical sidewalls around each island core. The logic circuitry blocks light from the core so light is primarily only sensed by the sidewalls.

    摘要翻译： 公开了一种用于光电二极管阵列的方法和结构，该阵列包括多个光电二极管芯，沿芯的外部的感光侧壁，芯之上的逻辑电路，分离芯的沟槽和沟槽中的透明材料。 利用本发明，侧壁垂直于接收入射光的光电二极管的表面。 感光侧壁包括当用光照射时引起电子转移的结区域。 侧壁包围围绕每个岛芯的四个垂直侧壁。 逻辑电路阻挡来自芯的光，因此光仅主要由侧壁感测。

    Method of fabricating a microelectromechanical system (MEMS) switch
    25.
    发明授权
    Method of fabricating a microelectromechanical system (MEMS) switch 失效
    制造微机电系统（MEMS）开关的方法

    公开(公告)号：US07657995B2

    公开(公告)日：2010-02-09

    申请号：US11776835

    申请日：2007-07-12

    申请人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01H11/00 ,  H01H65/00

    CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

    摘要： A method of fabricating a MEMS switch that is fully integratable in a semiconductor fabrication line. The method consists of forming two posts, each end thereof terminating in a cap; a rigid movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; forming upper and lower electrode pairs and upper and lower interconnect wiring lines connected and disconnected by the rigid movable conductive plate. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines.

    摘要翻译： 一种制造可在半导体制造生产线中完全集成的MEMS开关的方法。 该方法包括形成两个柱，其每端终止于盖中; 刚性可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松散地连接到引导柱; 形成上下电极对以及由刚性可移动导电板连接和断开的上下互连布线。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。

    Structure and method of fabricating a hinge type MEMS switch
    26.
    发明授权
    Structure and method of fabricating a hinge type MEMS switch 有权
    制造铰链式MEMS开关的结构和方法

    公开(公告)号：US07348870B2

    公开(公告)日：2008-03-25

    申请号：US10905449

    申请日：2005-01-05

    申请人： Louis C. Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

    发明人： Louis C. Hsu ,  Timothy Dalton ,  Lawrence Clevenger ,  Carl Radens ,  Kwong Hon Wong ,  Chih-Chao Yang

    IPC分类号： H01H51/22

    CPC分类号： H01H59/0009 ,  H01H1/20 ,  H01H2001/0084 ,  H01H2001/0089 ,  Y10T29/49105 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49204 ,  Y10T29/49208

    摘要： A hinge type MEMS switch that is fully integratable within a semiconductor fabrication process, such as a CMOS, is described. The MEMS switch constructed on a substrate consists of two posts, each end thereof terminating in a cap; a movable conductive plate having a surface terminating in a ring in each of two opposing edges, the rings being loosely connected to guiding posts; an upper and lower electrode pairs; and upper and lower interconnect wiring lines connected and disconnected by the movable conductive plate. When in the energized state, a low voltage level is applied to the upper electrode pair, while the lower electrode pair is grounded. The conductive plate moves up, shorting two upper interconnect wirings lines. Conversely, the conductive plate moves down when the voltage is applied to the lower electrode pair, while the upper electrode pair is grounded, shorting the two lower interconnect wiring lines and opening the upper wiring lines. The MEMS switch thus formed generates an even force that provides the conductive plate with a translational movement, with the displacement being guided by the two vertical posts.

    摘要翻译： 描述了在诸如CMOS之类的半导体制造工艺中可完全集成的铰链式MEMS开关。 构造在基板上的MEMS开关由两个柱构成，每个端部终止于盖; 可移动导电板，其表面终止于两个相对边缘中的每一个中的环中，所述环松动地连接到引导柱; 上下电极对; 以及由可动导电板连接和断开的上下互连布线。 当处于通电状态时，低电压电平施加到上电极对，而下电极对接地。 导电板向上移动，使两条上部互连线路短路。 相反，当电压施加到下电极对时，导电板向下移动，而上电极对接地，使两个下互连布线短路并打开上布线。 由此形成的MEMS开关产生均匀的力，其为导电板提供平移运动，位移由两个垂直柱引导。

    Method of forming nitride films with high compressive stress for improved PFET device performance
    29.
    发明授权
    Method of forming nitride films with high compressive stress for improved PFET device performance 失效
    形成具有高压缩应力的氮化物薄膜以提高PFET器件性能的方法

    公开(公告)号：US07462527B2

    公开(公告)日：2008-12-09

    申请号：US11160705

    申请日：2005-07-06

    申请人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    发明人： Richard A. Conti ,  Ronald P. Bourque ,  Nancy R. Klymko ,  Anita Madan ,  Michael C. Smits ,  Roy H. Tilghman ,  Kwong Hon Wong ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/3185 ,  H01L21/823828 ,  H01L29/7843

    摘要： A method is provided for making a FET device in which a nitride layer overlies the PFET gate structure, where the nitride layer has a compressive stress with a magnitude greater than about 2.8 GPa. This compressive stress permits improved device performance in the PFET. The nitride layer is deposited using a high-density plasma (HDP) process, wherein the substrate is disposed on an electrode to which a bias power in the range of about 50 W to about 500 W is supplied. The bias power is characterized as high-frequency power (supplied by an RF generator at 13.56 MHz). The FET device may also include NFET gate structures. A blocking layer is deposited over the NFET gate structures so that the nitride layer overlies the blocking layer; after the blocking layer is removed, the nitride layer is not in contact with the NFET gate structures. The nitride layer has a thickness in the range of about 300-2000 Å.

    摘要翻译： 提供了一种用于制造其中氮化物层覆盖PFET栅极结构的FET器件的方法，其中氮化物层具有大于约2.8GPa的量级的压缩应力。 这种压应力允许改进PFET中的器件性能。 使用高密度等离子体（HDP）工艺沉积氮化物层，其中衬底设置在供给约50W至约500W范围内的偏置功率的电极上。 偏置功率被表征为高频功率（由13.56MHz的RF发生器提供）。 FET器件还可以包括NFET栅极结构。 在NFET栅极结构上沉积阻挡层，使得氮化物层覆盖阻挡层; 在去除阻挡层之后，氮化物层不与NFET栅极结构接触。 氮化物层的厚度在约300-2000埃的范围内。