公开(公告)号：US07183163B2

公开(公告)日：2007-02-27

申请号：US10824016

申请日：2004-04-13

申请人： Dana Lee ,  Bomy Chen

发明人： Dana Lee ,  Bomy Chen

IPC分类号： H01L29/788 ,  H01L21/8238 ,  H01L21/336

CPC分类号： G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336

摘要： A method of making an isolation-less, contact-less array of bi-directional read/program non-volatile memory cells is disclosed. Each memory cell has two stacked gate floating gate transistors, with a switch transistor there between. The source/drain lines of the cells and the control gate lines of the stacked gate floating gate transistors in the same column are connected together. The gate of the switch transistors in the same row are connected together. Spaced apart trenches are formed in a substrate in a first direction. Floating gates are formed in the trenches, along the side wall of the trenches. A buried source/bit line is formed at the bottom of each trench. A control gate common to both floating gates is also formed in each trench insulated from the floating gates, capacitively coupled thereto, and insulated from the buried source/bit line. Transistor gates parallel to one another are formed in a second direction, substantially perpendicular to the first direction on the planar surface of the substrate. In one embodiment, openings between the rows of transistor gates are used to cut the floating gates in the trenches, without cutting the control gates.

摘要翻译： 公开了制造双向读/程序非易失性存储单元的无隔离，无接触阵列的方法。 每个存储单元具有两个堆叠栅极浮栅晶体管，其间具有开关晶体管。 单元的源极/漏极线和同一列中的堆叠栅极浮置栅极晶体管的控制栅极线连接在一起。 同一行的开关晶体管的栅极连接在一起。 在第一方向上在基板上形成间隔开的沟槽。 沿着沟槽的侧壁在沟槽中形成浮动栅极。 在每个沟槽的底部形成埋入的源极/位线。 两个浮动栅极共用的控制栅极也形成在与浮动栅极绝缘的每个沟槽中，电容耦合到该栅极并且与掩埋源极/位线绝缘。 在彼此平行的晶体管栅极形成在基板的平坦表面上基本上垂直于第一方向的第二方向上。 在一个实施例中，晶体管栅极行之间的开口用于切割沟槽中的浮动栅极而不切断控制栅极。

公开(公告)号：US07119396B2

公开(公告)日：2006-10-10

申请号：US10962008

申请日：2004-10-08

申请人： Bomy Chen ,  Dana Lee ,  Yaw Wen Hu ,  Bing Yeh

发明人： Bomy Chen ,  Dana Lee ,  Yaw Wen Hu ,  Bing Yeh

IPC分类号： H01L29/792

CPC分类号： H01L27/115 ,  H01L21/28114 ,  H01L27/11568 ,  H01L29/66553

摘要： A method of forming a memory device (and the resulting device) by forming an electron trapping dielectric material over a substrate, forming conductive material over the dielectric material, forming a spacer of material over the conductive material, removing portions of the dielectric material and the conductive material to form segments thereof disposed underneath the spacer of material, forming first and second spaced-apart regions in the substrate having a second conductivity type different from that of the substrate, with a channel region extending between the first and second regions, with the segments of the dielectric and first conductive materials being disposed over a first portion of the channel region for controlling a conductivity thereof, and forming a second conductive material over and insulated from a second portion of the channel region for controlling a conductivity thereof.

摘要翻译： 一种通过在衬底上形成电子捕获电介质材料形成存储器件（和所得器件）的方法，在电介质材料上形成导电材料，在导电材料上形成材料间隔物，去除电介质材料的部分和 导电材料以形成位于材料间隔物下方的段，在衬底中形成具有不同于衬底的第二导电类型的第一和第二间隔开的区域，沟道区域在第一和第二区域之间延伸， 电介质和第一导电材料的片段设置在沟道区域的第一部分上，用于控制其导电率，并且在沟道区域的第二部分上形成第二导电材料并与之绝缘以控制其导电性。

公开(公告)号：US20060071255A1

公开(公告)日：2006-04-06

申请号：US10949778

申请日：2004-09-24

申请人： Bomy Chen ,  Dana Lee ,  June Han

发明人： Bomy Chen ,  Dana Lee ,  June Han

IPC分类号： H01L29/94

CPC分类号： H01L27/11507 ,  G11C11/22 ,  G11C11/221 ,  H01L27/11502 ,  H01L28/55

摘要： A ferroelectric memory cell has a semiconductor substrate of a first conductivity type having a first region and a second region with each being of a second conductivity type, with a channel region therebetween. The first region and the second region are aligned in a first direction. A gate dielectric is over at least a portion of the channel region. A gate is over the gate dielectric, with the gate extending in a direction transverse to the first direction termination at a termination point not overlapping the first region, the second region and the channel region. A ferroelectric capacitor is at the termination point. The ferroelectric capacitor has a first end and a second end with the first end connected to the gate. The ferroelectric memory cell has three terminals: the first region, the second region, and the second end. In another embodiment, an insulator is over at least a portion of the first region. The gate has one end over the gate dielectric and extends over the insulator terminating at a termination point. A ferroelectric capacitor is connected to the termination point, which lies over a portion of the first region.

摘要翻译： 铁电存储单元具有第一导电类型的半导体衬底，其具有第一区域和第二区域，每个具有第二导电类型，其间具有沟道区域。 第一区域和第二区域沿第一方向排列。 栅极电介质在沟道区域的至少一部分之上。 栅极在栅极电介质上方，栅极在与第一区域，第二区域和沟道区域不重叠的终止点处沿横向于第一方向终止的方向延伸。 铁电电容器处于终端点。 铁电电容器具有第一端和第二端，第一端连接到栅极。 铁电存储单元具有三个端子：第一区域，第二区域和第二端子。 在另一个实施例中，绝缘体在第一区域的至少一部分之上。 栅极的一端位于栅极电介质上，并在绝缘体上延伸，终止于终止点。 铁电电容器连接到位于第一区域的一部分上的终止点。

公开(公告)号：US06960803B2

公开(公告)日：2005-11-01

申请号：US10693067

申请日：2003-10-23

申请人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

发明人： Dana Lee ,  Wen-Juei Lu ,  Felix Ying-Kit Tsui

IPC分类号： H01L21/336 ,  H01L21/768 ,  H01L29/76

CPC分类号： H01L21/76895

摘要： A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjacent to each island and overlapping each other and overlapping with the conductive spacer adjacent to the structure. The contact to the landing pad is on the conductive spacers adjacent to the islands and spaced apart from the structure.

摘要翻译： 用作与半导体器件中的结构相邻的导电间隔件的接触件的接合焊盘包括两个岛，每个岛基本上为矩形并且彼此间隔开并且与该结构隔开。 导电间隔件与每个岛相邻并且彼此重叠并与邻近结构的导电间隔物重叠。 与着陆垫的接触在邻近岛的导电间隔物上并且与结构间隔开。

公开(公告)号：US20050219914A1

公开(公告)日：2005-10-06

申请号：US10814443

申请日：2004-03-30

申请人： Vishal Sarin ,  Hieu Tran ,  Dana Lee

发明人： Vishal Sarin ,  Hieu Tran ,  Dana Lee

IPC分类号： G11C7/00 ,  G11C7/12 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/0433 ,  G11C7/12 ,  G11C16/10

摘要： The memory system includes a bitline leakage current compensation circuit for compensating for leakage current in an operational memory array by measuring the leakage current in a non-operational memory array or a dummy memory array and providing a feedback signal to a current source or providing the compensation current.

摘要翻译： 存储器系统包括位线泄漏电流补偿电路，用于通过测量非操作存储器阵列或虚拟存储器阵列中的漏电流来补偿操作存储器阵列中的漏电流，并向电流源提供反馈信号或提供补偿 当前。

公开(公告)号：US20050213386A1

公开(公告)日：2005-09-29

申请号：US11078562

申请日：2005-02-28

申请人： Amitay Levi ,  Pavel Klinger ,  Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

发明人： Amitay Levi ,  Pavel Klinger ,  Bomy Chen ,  Hieu Tran ,  Dana Lee ,  Jack Frayer

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  G11C16/04

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42328 ,  H01L29/7885

摘要： A nonvolatile memory cell having a floating gate for the storage of charges thereon has a control gate and a separate erase gate. The cell is programmed by hot channel electron injection and is erased by poly to poly Fowler-Nordheim tunneling. A method for making an array of unidirectional cells in a planar substrate, as well as an array of bidirectional cells in a substrate having a trench, is disclosed. An array of such cells and a method of making such an array is also disclosed.

公开(公告)号：US20050045940A1

公开(公告)日：2005-03-03

申请号：US10653015

申请日：2003-08-28

申请人： Bomy Chen ,  Dana Lee ,  Hieu Tran

发明人： Bomy Chen ,  Dana Lee ,  Hieu Tran

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788

CPC分类号： H01L27/11556 ,  H01L27/115 ,  H01L29/42336 ,  H01L29/7885

摘要： An array of floating gate memory cells, and a method of making same, where each pair of memory cells includes a pair of trenches formed into a surface of a semiconductor substrate, with a strip of the substrate disposed therebetween, a source region formed in the substrate strip, a pair of drain regions, a pair of channel regions each extending between the source region and one of the drain regions, a pair of floating gates each disposed in one of the trenches, and a pair of control gates. Each channel region has a first portion disposed in the substrate strip and extending along one of the trenches, a second portion extending underneath the one trench, a third portion extending along the one trench, and a fourth portion extending along the substrate surface and under one of the control gates.

摘要翻译： 一种浮动栅极存储单元的阵列及其制造方法，其中每对存储单元包括形成在半导体衬底的表面中的一对沟槽，其中衬底的条带设置在其间，源区域形成在 衬底条，一对漏极区，一对沟道区，每个沟道区各自在源极区和漏极区之一之间延伸;一对浮置栅极，分别设置在一个沟槽中，以及一对控制栅极。 每个通道区域具有设置在衬底条中并沿​​其中一个沟槽延伸的第一部分，在一个沟槽下面延伸的第二部分，沿该沟槽延伸的第三部分，以及沿衬底表面延伸的第四部分 的控制门。

公开(公告)号：US20140040681A1

公开(公告)日：2014-02-06

申请号：US13565650

申请日：2012-08-02

申请人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

发明人： Jonathan Wolfman ,  Dana Lee ,  Jonathan Hsu

IPC分类号： G06F12/02 ,  G06F11/00

CPC分类号： G06F11/1048 ,  G01R31/3171 ,  G06F11/07 ,  G06F11/076 ,  G06F11/30 ,  G06F12/02 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/16 ,  G06F2212/7211 ,  G11C16/04 ,  G11C16/34 ,  G11C16/349 ,  G11C2029/0409 ,  H04L1/0061

摘要： A system for improving the management and usage of blocks based on intrinsic endurance may be used to improve memory usage for flash memory, such as a memory card. The overall card endurance may be extended by cycling blocks with higher intrinsic endurance over the lowest endurance target of the worst block. This may be accomplished by managing blocks with different intrinsic endurance values internally or by partitioning the blocks with different intrinsic endurance values externally for different usage.

摘要翻译： 可以使用用于改善基于固有耐力的块的管理和使用的系统来改善诸如存储卡的闪存的存储器使用。 整体卡耐力可以通过在最差块的最低耐力目标下具有较高内在耐力的循环块来延长。 这可以通过内部管理具有不同内在耐力值的块来实现，或者通过外部对不同的内在耐力值进行分区，以实现不同的使用。

公开(公告)号：US20140029357A1

公开(公告)日：2014-01-30

申请号：US13559377

申请日：2012-07-26

申请人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

发明人： Dana Lee ,  Yi-Chieh Chen ,  Farookh Moogat

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C16/30

摘要： A non-volatile memory with multiple memory dice manages simultaneous operations so as to not exceed a system power capacity. A load signal bus is pulled up with a strength proportional to the system power capacity. Each die has a driver to pull down the bus by an amount corresponding to its degree of power need as estimated by a state machine of the die. The bus therefore provides a load signal that serves as arbitration between the system power capacity and the cumulative loads of the individual dice. The load signal is therefore at a high state when the system power capacity is not exceeded; otherwise it is at a low state. When a die wishes to perform an operation and requests a certain amount of power, it drives the bus accordingly and its state machine either proceeds with the operation or not, depending on the load signal.

摘要翻译： 具有多个存储器骰子的非易失性存储器管理同时操作，以便不超过系统功率容量。 负载信号总线以与系统功率容量成比例的强度被拉高。 每个模具具有一个驱动器，用于将总线的数量下降一定量，与模具状态机所估计的功率需求量相对应。 因此，总线提供负载信号，用作系统功率容量和单个骰子的累积负载之间的仲裁。 因此，当不超过系统功率容量时，负载信号处于高电平状态; 否则处于低状态。 当模具希望执行操作并请求一定量的电力时，它相应地驱动总线，并且其状态机根据负载信号进行操作。

公开(公告)号：US20130346805A1

公开(公告)日：2013-12-26

申请号：US13529522

申请日：2012-06-21

申请人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

发明人： Steven T. Sprouse ,  Alexandra Bauche ,  Yichao Huang ,  Jian Chen ,  Jianmin Huang ,  Dana Lee

IPC分类号： G06F11/28

CPC分类号： G11C16/3418 ,  G11B20/18 ,  G11B20/1883 ,  G11C16/3427 ,  G11C16/3431

摘要： A method and system have been described for counteracting and correcting for read disturb effects in blocks of flash memory. The method may include the step of a controller of the memory system performing a read scrub scan on only a portion of one targeted word line in a block at desired intervals. The controller may calculate whether a read scrub scan is necessary based on a probabilistic determination that is calculated in response to each received host read command. The controller may then place a block associated with the targeted word line into a refresh queue if a number of errors are detected in the targeted word line that meets or exceeds a predetermined threshold. The block refresh process may include copying the data from the block into a new block during a background operation.

摘要翻译： 已经描述了用于抵消和校正闪速存储器块中的读取干扰效应的方法和系统。 该方法可以包括存储器系统的控制器的步骤，其以期望的间隔仅在块中的一个目标字线的一部分上执行读取擦除扫描。 控制器可以基于响应于每个接收的主机读取命令而计算的概率确定来计算是否需要读取擦除扫描。 然后，如果在满足或超过预定阈值的目标字线中检测到多个错误，则控制器然后可以将与目标字线相关联的块放置到刷新队列中。 块刷新过程可以包括在后台操作期间将数据从块复制到新块中。