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    Smartcard interconnect
    21.
    发明授权
    Smartcard interconnect 失效
    智能卡互连

    公开(公告)号：US08348171B2

    公开(公告)日：2013-01-08

    申请号：US13030993

    申请日：2011-02-18

    申请人： Paul Amadeo ,  Jose Flores ,  Robert Kraft

    发明人： Paul Amadeo ,  Jose Flores ,  Robert Kraft

    IPC分类号： G06K19/06

    CPC分类号： G06K19/07749 ,  G06K19/07752 ,  G06K19/07779 ,  G06K19/07781 ,  Y10T29/49162

    摘要： A smart card inlay and method for assembling the same are provided. The method includes attaching a first trace to a substrate, attaching a second trace to the substrate, attaching an antenna wire to the substrate, coupling a first end of the antenna wire to a first area of the first trace, and coupling a second end of the antenna wire to a first area of the second trace. A second area of the first trace and a second area of the second trace are configured to be coupled to an integrated circuit (IC) or IC module, and the first area of the first trace is located away from the second area of the first trace and the first area of the second trace is located away from the second area of the second trace.

    摘要翻译： 提供了一种用于组装智能卡嵌体和方法。 该方法包括将第一迹线附接到衬底，将第二迹线附接到衬底，将天线连接到衬底，将天线线的第一端耦合到第一迹线的第一区域，以及将第 天线连接到第二迹线的第一区域。 第一迹线的第二区域和第二迹线的第二区域被配置为耦合到集成电路（IC）或IC模块，并且第一迹线的第一区域位于远离第一迹线的第二区域 并且第二迹线的第一区域位于远离第二迹线的第二区域的位置。

    FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION
    23.
    发明申请
    FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION 有权
    在碳化硅蚀刻停止沉积期间形成硅氧化物界面层以促进更好的电介质粘结

    公开(公告)号：US20080283975A1

    公开(公告)日：2008-11-20

    申请号：US11750669

    申请日：2007-05-18

    申请人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    发明人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    IPC分类号： H01L21/31 ,  H01L23/58

    CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834

    摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

    摘要翻译： 根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。 在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。 该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善 与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

    Method for patterning sub-lithographic features in semiconductor manufacturing
    24.
    发明授权
    Method for patterning sub-lithographic features in semiconductor manufacturing 有权
    在半导体制造中图案化亚光刻特征的方法

    公开(公告)号：US07300883B2

    公开(公告)日：2007-11-27

    申请号：US10930228

    申请日：2004-08-31

    申请人： Francis G. Celii ,  Brian A. Smith ,  James Blatchford ,  Robert Kraft

    发明人： Francis G. Celii ,  Brian A. Smith ,  James Blatchford ,  Robert Kraft

    IPC分类号： H01L21/336 ,  H01L21/302 ,  H01L21/461 ,  H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.

    摘要翻译： 公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。 例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。 然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案， ，尽管对于更宽的光刻宽度（LW）。 图案从光致抗蚀剂（30）转移到BARC层（29）。 然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。 然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。 硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。

    Energy beam treatment to improve the hermeticity of a hermetic layer
    25.
    发明申请
    Energy beam treatment to improve the hermeticity of a hermetic layer 审中-公开
    能量束处理以提高密封层的气密性

    公开(公告)号：US20060264028A1

    公开(公告)日：2006-11-23

    申请号：US11134566

    申请日：2005-05-20

    申请人： Laura Matz ,  Ting Tsui ,  Robert Kraft

    发明人： Laura Matz ,  Ting Tsui ,  Robert Kraft

    IPC分类号： H01L21/469

    CPC分类号： H01L21/3105 ,  H01L21/76825 ,  H01L21/76829 ,  H01L23/5329 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a process for increasing the hermeticity of a hermetic layer, a method for manufacturing an interconnect structure, and a method for manufacturing an integrated circuit. The process for increasing the hermeticity of the hermetic layer, without limitation, includes providing a hermetic layer over a substrate (160), the hermetic layer having a initial hermeticity, and subjecting the hermetic layer to an energy beam, thereby causing the initial hermeticity to improve (170).

    摘要翻译： 本发明提供一种增加气密层的气密性的方法，一种互连结构的制造方法以及集成电路的制造方法。 增加密封层的气密性而不是限制的方法包括在衬底（160）上提供密封层，密封层具有初始密封性，并且使密封层经受能量束，从而使初始气密性 改善（170）。

    Method for patterning sub-lithographic features in semiconductor manufacturing
    26.
    发明申请
    Method for patterning sub-lithographic features in semiconductor manufacturing 有权
    在半导体制造中图案化亚光刻特征的方法

    公开(公告)号：US20060046498A1

    公开(公告)日：2006-03-02

    申请号：US10930228

    申请日：2004-08-31

    申请人： Francis Celii ,  Brian Smith ,  James Blatchford ,  Robert Kraft

    发明人： Francis Celii ,  Brian Smith ,  James Blatchford ,  Robert Kraft

    IPC分类号： H01L21/00

    CPC分类号： H01L21/28123 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

    摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.

    摘要翻译： 公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。 例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。 然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案， ，尽管对于更宽的光刻宽度（LW）。 图案从光致抗蚀剂（30）转移到BARC层（29）。 然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。 然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。 硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。

    Dry etch process for small-geometry metal gates over thin gate dielectric
    28.
    发明授权
    Dry etch process for small-geometry metal gates over thin gate dielectric 有权
    用于薄栅电介质上的小几何金属栅的干法蚀刻工艺

    公开(公告)号：US06261934B1

    公开(公告)日：2001-07-17

    申请号：US09206074

    申请日：1998-12-04

    申请人： Robert Kraft ,  Antonio L. P. Rotondaro

    发明人： Robert Kraft ,  Antonio L. P. Rotondaro

    IPC分类号： H01L21306

    CPC分类号： H01L21/32136

    摘要： Fabrication of metal-on-conductive-diffusion-barrier-on-gate-dielectric structures is done by: etching the metal, by plasma-assisted anisotropic etching, down to and into the barrier metal; and then etching the remainder of the barrier layer by a dry chemical-downstream-etching process, during which the barrier layer is not exposed to ion bombardment. In the case of tungsten over titanium nitride, high selectivity and good profiles are preferably obtained, by: during the tungsten etch, using a combination of low temperature, relatively low bias, and the addition of nitrogen; and during the titanium nitride etch, using a chemical downstream etch instead of the conventional wet etch (in boiling H2SO4). (This allows better control of undercutting, and eliminates wet strip process.)

    摘要翻译： 金属导电扩散阻挡栅极 - 介电结构的制造通过以下方式进行：通过等离子体辅助的各向异性蚀刻蚀刻金属，向下并进入阻挡金属; 然后通过干化学下游蚀刻工艺蚀刻阻挡层的其余部分，在此期间阻挡层不暴露于离子轰击。 在氮化钛上的钨的情况下，优选地通过以下方式获得高选择性和良好的分布：在钨蚀刻期间，使用低温，相对低的偏压和氮的添加的组合; 并且在氮化钛蚀刻期间，使用化学下游蚀刻而不是常规湿法蚀刻（在沸腾的H 2 SO 4中）。 （这样可以更好地控制底切，并消除湿法处理。）

    VARIABLE PITCH MANDREL WOUND ANTENNAS AND SYSTEMS AND METHODS OF MAKING SAME
    30.
    发明申请
    VARIABLE PITCH MANDREL WOUND ANTENNAS AND SYSTEMS AND METHODS OF MAKING SAME 失效
    可变的人造天线和系统及其制造方法

    公开(公告)号：US20110205140A1

    公开(公告)日：2011-08-25

    申请号：US12950636

    申请日：2010-11-19

    申请人： Paul Amadeo ,  Jose Flores ,  Robert Kraft

    发明人： Paul Amadeo ,  Jose Flores ,  Robert Kraft

    IPC分类号： H01Q7/00 ,  H01P11/00

    CPC分类号： H01Q7/00 ,  G06K19/07779 ,  G06K19/07781 ,  H01F41/074 ,  H01F41/098 ,  H01Q1/2225 ,  Y10T29/49016

    摘要： A system and method for fabricating a mandrel wound antenna are provided. The method includes securing a first end of a wire to a first portion of a mandrel tool, where the mandrel tool includes a faceplate supporting a plurality of posts, and the posts arranged and disposed to define non-overlapping circumferential patterns. The method also includes wrapping the wire around outer peripheries of the plurality of posts to form non-overlapping wire coils around the plurality of circumferential patterns to provide an antenna. The method further includes securing a second end of the wire to a second portion of the mandrel tool, cutting the wire in proximity to the second end, attaching the antenna to a substrate separate from the faceplate, and detaching the antenna from the faceplate.

    摘要翻译： 提供了一种用于制造心轴缠绕天线的系统和方法。 该方法包括将线的第一端固定到心轴工具的第一部分，其中心轴工具包括支撑多个柱的面板，以及布置和设置以限定非重叠圆周图案的柱。 该方法还包括围绕多个柱的外周缠绕线以在多个圆周图案周围形成不重叠的线圈以提供天线。 该方法还包括将线的第二端固定到心轴工具的第二部分，将线接近第二端切割，将天线连接到与面板分离的基底，以及将天线从面板上分离。