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    Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion
    1.
    发明授权
    Formation of a silicon oxide interface layer during silicon carbide etch stop deposition to promote better dielectric stack adhesion 有权
    在碳化硅蚀刻停止沉积期间形成氧化硅界面层以促进更好的介电堆叠粘附

    公开(公告)号：US07682989B2

    公开(公告)日：2010-03-23

    申请号：US11750669

    申请日：2007-05-18

    申请人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    发明人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834

    摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

    摘要翻译： 根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。 在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。 该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善 与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

    FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION
    2.
    发明申请
    FORMATION OF A SILICON OXIDE INTERFACE LAYER DURING SILICON CARBIDE ETCH STOP DEPOSITION TO PROMOTE BETTER DIELECTRIC STACK ADHESION 有权
    在碳化硅蚀刻停止沉积期间形成硅氧化物界面层以促进更好的电介质粘结

    公开(公告)号：US20080283975A1

    公开(公告)日：2008-11-20

    申请号：US11750669

    申请日：2007-05-18

    申请人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    发明人： Laura M. Matz ,  Ting Y. Tsui ,  Thad E. Briggs ,  Robert Kraft

    IPC分类号： H01L21/31 ,  H01L23/58

    CPC分类号： H01L21/3148 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31608 ,  H01L21/3185 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834

    摘要： In accordance with the present teachings, semiconductor devices and methods of making semiconductor devices and dielectric stack in an integrated circuit are provided. The method of forming a dielectric stack in an integrated circuit can include providing a semiconductor structure including one or more copper interconnects and forming an etch stop layer over the semiconductor structure in a first processing chamber. The method can also include forming a thin silicon oxide layer over the etch stop layer in the first processing chamber and forming an ultra low-k dielectric layer over the thin silicon oxide layer in a second processing chamber, wherein forming the thin silicon oxide layer improves adhesion between the etch stop layer and the ultra low-k dielectric as compared to a dielectric stack that is devoid of the thin silicon oxide layer between the etch stop layer and the ultra low-k dielectric.

    摘要翻译： 根据本教导，提供半导体器件以及在集成电路中制造半导体器件和电介质叠层的方法。 在集成电路中形成电介质堆叠的方法可以包括提供包括一个或多个铜互连的半导体结构，并在第一处理室中在半导体结构之上形成蚀刻停止层。 该方法还可以包括在第一处理室中的蚀刻停止层之上形成薄的氧化硅层，并在第二处理室中的薄氧化硅层上形成超低k电介质层，其中形成薄氧化硅层改善 与在蚀刻停止层和超低k电介质之间没有薄氧化硅层的电介质堆叠相比，蚀刻停止层和超低k电介质之间的粘附性。

    Energy beam treatment to improve packaging reliability
    3.
    发明授权
    Energy beam treatment to improve packaging reliability 有权
    能量束处理提高包装可靠性

    公开(公告)号：US07678713B2

    公开(公告)日：2010-03-16

    申请号：US11196985

    申请日：2005-08-04

    申请人： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

    发明人： Ting Y. Tsui ,  Andrew McKerrow ,  Satyavolu Srinivas Papa Rao ,  Robert Kraft

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L21/76825

    摘要： The present invention provides a process for improving the hardness and/or modulus of elasticity of a dielectric layer and a method for manufacturing an integrated circuit. The process for improving the hardness and/or modulus of elasticity of a dielectric layer, among other steps, includes providing a dielectric layer having a hardness and a modulus of elasticity, and subjecting the dielectric layer to an energy beam, thereby causing the hardness or modulus of elasticity to increase in value.

    摘要翻译： 本发明提供一种提高介电层的硬度和/或弹性模量的方法以及集成电路的制造方法。 提供电介质层的硬度和/或弹性模量的方法以及其它步骤包括提供具有硬度和弹性模量的电介质层，以及使电介质层经受能量束，从而使硬度或 弹性模量增加值。

    Systems and methods that selectively modify liner induced stress
    4.
    发明授权
    Systems and methods that selectively modify liner induced stress 有权
    系统和方法选择性地修改衬垫引起的应力

    公开(公告)号：US07442597B2

    公开(公告)日：2008-10-28

    申请号：US11049275

    申请日：2005-02-02

    申请人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    发明人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

    摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

    Methods to facilitate etch uniformity and selectivity
    5.
    发明授权
    Methods to facilitate etch uniformity and selectivity 有权
    促进蚀刻均匀性和选择性的方法

    公开(公告)号：US07341941B2

    公开(公告)日：2008-03-11

    申请号：US11207493

    申请日：2005-08-19

    申请人： Ting Y. Tsui ,  Jeannette M. Jacques ,  Robert Kraft ,  Ping Jiang

    发明人： Ting Y. Tsui ,  Jeannette M. Jacques ,  Robert Kraft ,  Ping Jiang

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76825 ,  H01L21/76807

    摘要： A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.

    摘要翻译： 用基于能量的工艺制造半导体器件，其改变镶嵌工艺内的电介质层的蚀刻速率。 第一互连层形成在半导体本体上。 第一介电层形成在第一互连层上。 改变第一介电层的蚀刻速率。 在第一电介质层上形成第二电介质层。 然后改变第二电介质层的蚀刻速率。 执行沟槽蚀刻以在第二介电层内形成沟槽。 执行通孔蚀刻以在第一介电层内形成通孔腔。 空腔填充有导电材料，然后平坦化以除去多余的填充材料。

    SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS
    6.
    发明申请
    SYSTEMS AND METHODS THAT SELECTIVELY MODIFY LINER INDUCED STRESS 有权
    选择性修改衬里诱发应力的系统和方法

    公开(公告)号：US20090017588A1

    公开(公告)日：2009-01-15

    申请号：US12235766

    申请日：2008-09-23

    申请人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    发明人： Ting Y. Tsui ,  Satyavolu S. Papa Rao ,  Haowen Bu ,  Robert Kraft

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/76829 ,  H01L21/76825 ,  H01L21/823807 ,  H01L21/823828

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively apply strain to multiple regions of a semiconductor device. A semiconductor device having one or more regions is provided (102). A strain inducing liner is formed over the semiconductor device (104). A selection mechanism, such as a layer of photoresist or UV reflective coating is applied to the semiconductor device to select a region (106). The selected region is treated with a stress altering treatment that alters a type and/or magnitude of stress produced by the selected region (108).

    摘要翻译： 本发明通过提供选择性地将应变应用于半导体器件的多个区域的制造方法来促进半导体制造。 提供具有一个或多个区域的半导体器件（102）。 应变诱导衬垫形成在半导体器件（104）上。 将诸如光致抗蚀剂层或UV反射涂层的选择机构施加到半导体器件以选择区域（106）。 选择的区域用改变由选定区域（108）产生的应力的类型和/或大小的应力改变处理来处理。

    Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability
    7.
    发明申请
    Silicon nitride/oxygen doped silicon carbide etch stop bi-layer for improved interconnect reliability 审中-公开
    氮化硅/氧掺杂碳化硅蚀刻停止双层以提高互连可靠性

    公开(公告)号：US20080014739A1

    公开(公告)日：2008-01-17

    申请号：US11475924

    申请日：2006-06-28

    申请人： Laura M. Matz ,  Asad Haider ,  Robert Kraft

    发明人： Laura M. Matz ,  Asad Haider ,  Robert Kraft

    IPC分类号： H01L21/4763 ,  H01L23/52 ,  H01L23/48 ,  H01L29/40

    CPC分类号： H01L23/53295 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In accordance with the invention, there are semiconductor devices and methods for making semiconductor devices and film stacks in an integrated circuits. The method of making a semiconductor device can comprise forming a semiconductor structure comprising at least one copper interconnect, forming an etch stop bi-layer comprising a first layer and a second layer, wherein the first layer comprising silicon nitride is disposed over the semiconductor structure comprising at least one copper interconnect, and the second layer comprising silicon oxy-carbide is disposed over the first layer, and depositing a dielectric layer over the etch stop bi-layer.

    摘要翻译： 根据本发明，存在用于在集成电路中制造半导体器件和薄膜叠层的半导体器件和方法。 制造半导体器件的方法可以包括形成包括至少一个铜互连的半导体结构，形成包括第一层和第二层的蚀刻停止双层，其中包含氮化硅的第一层设置在半导体结构之上，包括 至少一个铜互连，并且包含碳化硅碳的第二层设置在第一层之上，并且在蚀刻停止双层上沉积介电层。