公开(公告)号：US5425810A

公开(公告)日：1995-06-20

申请号：US241254

申请日：1994-05-11

申请人： Richard A. Conti ,  David E. Kotecki ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

发明人： Richard A. Conti ,  David E. Kotecki ,  Donald L. Wilson ,  Justin W. Wong ,  Steven P. Zuhoski

IPC分类号： C23C16/44 ,  C23C16/455 ,  C23C16/00 ,  C23C16/12

CPC分类号： C23C16/45574 ,  C23C16/4407 ,  C23C16/45512

摘要： A removable gas injector design compatible for use in chemical vapor deposition reactors that allows proper mixing of the reactant gases, reduced cycle time associated with cleaning of gas injector components, and elimination of uncertainties associated with manual cleaning of the injector. A better reliability to the system due to the known condition of the nozzle after a clean is achieved.

摘要翻译： 适用于化学气相沉积反应器的可拆卸气体喷射器设计，其允许反应气体的适当混合，减少与气体喷射器部件的清洁有关的循环时间，以及消除与手动清洁喷射器有关的不确定性。 实现了清洁之后喷嘴的已知状况对系统的更好的可靠性。

公开(公告)号：US20120187522A1

公开(公告)日：2012-07-26

申请号：US13010041

申请日：2011-01-20

申请人： Michael V. Aquilino ,  Christopher V. Baiocco ,  Richard A. Conti ,  Daniel J. Jaeger ,  Vijay Narayanan

发明人： Michael V. Aquilino ,  Christopher V. Baiocco ,  Richard A. Conti ,  Daniel J. Jaeger ,  Vijay Narayanan

IPC分类号： H01L29/06 ,  G06F17/50 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L29/517

摘要： A substrate is provided. An STI trench is formed in the substrate. A fill material is formed in the STI trench and then planarized. The substrate is exposed to an oxidizing ambient, growing a liner at a bottom and sidewalls of the STI trench. The liner reduces the Vt-W effect in high-k metal gate devices.

摘要翻译： 提供基板。 在衬底中形成STI沟槽。 填充材料形成在STI沟槽中，然后平坦化。 将衬底暴露于氧化环境中，在STI沟槽的底部和侧壁处生长衬垫。 衬垫降低了高k金属栅极器件中的Vt-W效应。

公开(公告)号：US20090004869A1

公开(公告)日：2009-01-01

申请号：US12145915

申请日：2008-06-25

申请人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

发明人： Katherina Babich ,  Todd C. Bailey ,  Richard A. Conti ,  Ryan P. Deschner

IPC分类号： H01L21/302

CPC分类号： H01L21/266 ,  H01L21/26513 ,  Y10T428/24992

摘要： Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.

摘要翻译： 形成用于植入衬底的掩模和使用具有光刻胶的注入阻挡层进行植入的方法提供了较低的纵横比掩模，其在去除掩模期间对衬底中的沟槽隔离造成最小的损害。 在一个实施例中，形成掩模的方法包括：在衬底上沉积注入阻挡层; 在所述注入阻挡层上沉积光致抗蚀剂，所述注入阻挡层的密度大于所述光致抗蚀剂; 通过去除光致抗蚀剂的一部分以暴露植入物停止层，在光致抗蚀剂中形成图案; 并通过蚀刻将图案转移到植入物停止层中以形成掩模。 注入停止层可以包括：氢化碳化锗，氮化碳化锗，氟化锗碳化物和/或无定形锗碳氢化物（GeHX），其中X包括碳。 方法/掩模减少了植入过程中的散射，因为掩模具有比常规掩模更高的密度。

公开(公告)号：US06548357B2

公开(公告)日：2003-04-15

申请号：US10117869

申请日：2002-04-08

申请人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

发明人： Mary E. Weybright ,  Gary Bronner ,  Richard A. Conti ,  Ramachandra Divakaruni ,  Jeffrey Peter Gambino ,  Peter Hoh ,  Uwe Schroeder

IPC分类号： H01L21336

CPC分类号： H01L27/10894 ,  H01L21/76897 ,  H01L21/823456 ,  H01L27/1052 ,  H01L27/10873

摘要： Two different gate conductor dielectric caps are used in the array and support device regions so that the bitline contact can be fabricated in the array region, but a thinner hard mask can be used for better linewidth control in the support device region. The thinner dielectric cap is made into dielectric spacers in the array device regions during support mask etching. These dielectric spacers allow for the array gate conductor resist line to be made smaller than the final gate conductor linewidth. This widens the array gate conductor processing window. The second dielectric cap layer improves linewidth control for the support devices and the array devices. Two separate gate conductor lithography steps and gate conductor dielectric etches are carried out in the present invention to optimize the gate conductor linewidth control in the array and support device regions. The gate conductors in the array and support devices regions are etched simultaneously to reduce production cost. In additional embodiments of the invention, dual workfunction support device transistors with or without salicide can be fabricated with an array including borderless contacts.

摘要翻译： 在阵列和支撑器件区域中使用两个不同的栅极导体电介质盖，使得可以在阵列区域中制造位线接触，但是可以使用较薄的硬掩模用于支撑装置区域中的更好的线宽控制。 在支撑掩模蚀刻期间，将较薄的介质盖制成阵列器件区域中的电介质间隔物。 这些介质间隔物允许使阵列栅极导体抗蚀剂线小于最终的栅极导体线宽。 这扩大了阵列栅极导体处理窗口。 第二电介质盖层改善了支撑装置和阵列装置的线宽控制。 在本发明中执行两个单独的栅极导体光刻步骤和栅极导体介电蚀刻，以优化阵列和支撑装置区域中的栅极导体线宽控制。 阵列和支撑装置区域中的栅极导体被同时蚀刻以降低生产成本。 在本发明的另外的实施例中，可以用包括无边界触点的阵列来制造具有或不具有自对准硅的双功能功能支撑器件晶体管。

公开(公告)号：US06531412B2

公开(公告)日：2003-03-11

申请号：US09928209

申请日：2001-08-10

申请人： Richard A. Conti ,  Daniel C. Edelstein ,  Gill Yong Lee

发明人： Richard A. Conti ,  Daniel C. Edelstein ,  Gill Yong Lee

IPC分类号： H01C2131

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02112 ,  H01L21/02129 ,  H01L21/02205 ,  H01L21/02216 ,  H01L21/3122 ,  H01L21/31604 ,  H01L21/31625 ,  H01L21/31629 ,  H01L21/31633 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method is described for forming a low-k dielectric film, in particular, a pre-metal dielectric (PMD) on a semiconductor wafer which has good gap-filling characteristics. The method uses a thermal sub-atmospheric CVD process that includes a carbon-containing organometallic precusor such as TMCTS or OMCTS, an ozone-containing gas, and a source of dopants for gettering alkali elements and for lowering the reflow temperature of the dielectric while attaining the desired low-k and gap-filling properties of the dielectric film. Phosphorous is a preferred dopant for gettering alkali elements such as sodium. Additional dopants for lowering the reflow temperature include, but are not limited to boron, germanium, arsenic, fluorine or combinations thereof.

摘要翻译： 描述了一种形成低k电介质膜的方法，特别是在具有良好间隙填充特性的半导体晶片上的预金属电介质（PMD）。 该方法使用包括含碳有机金属预处理剂如TMCTS或OMCTS，含臭氧气体和用于吸收碱元素的掺杂剂源的热亚低温CVD工艺，并且在达到时降低电介质的回流温度 电介质膜的期望的低k和间隙填充性能。 磷是用于吸收碱元素如钠的优选掺杂剂。 用于降低回流温度的附加掺杂剂包括但不限于硼，锗，砷，氟或其组合。

公开(公告)号：US06429149B1

公开(公告)日：2002-08-06

申请号：US09511394

申请日：2000-02-23

申请人： Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Byeongju Park

发明人： Ashima B. Chakravarti ,  Richard A. Conti ,  Laertis Economikos ,  Byeongju Park

IPC分类号： H01L2131

CPC分类号： H01L21/02271 ,  C23C16/401 ,  H01L21/02129 ,  H01L21/02164 ,  H01L21/02337 ,  H01L21/31625

摘要： A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

摘要翻译： 所公开的方法使用在衬底上的掺杂氧化物膜的低压化学气相沉积（LPCVD）。 该方法包括以下步骤：在LPCVD反应器中提供衬底并将BTBAS和氧气流入LPCVD反应器以在衬底上反应以在衬底上沉积氧化物膜。 掺杂的前体流入LPCVD反应器以在氧化膜沉积在衬底上时掺杂氧化膜。 该方法在相对低的LPCVD反应温度下产生掺杂的氧化物膜。

公开(公告)号：US06335261B1

公开(公告)日：2002-01-01

申请号：US09584355

申请日：2000-05-31

申请人： Wesley Natzle ,  Richard A. Conti ,  Laertis Economikos ,  Thomas Ivers ,  George D. Papasouliotis

发明人： Wesley Natzle ,  Richard A. Conti ,  Laertis Economikos ,  Thomas Ivers ,  George D. Papasouliotis

IPC分类号： H01L2100

CPC分类号： H01L21/76224 ,  C23C16/045 ,  H01L21/30655 ,  H01L21/32136 ,  H01L21/764

摘要： A method is described for filling a high-aspect-ratio feature, in which compatible deposition and etching steps are performed in a sequence. The feature is formed as an opening in a substrate having a surface; a fill material is deposited at the bottom of the feature and on the surface of the substrate; deposition on the surface adjacent the feature causes formation of an overhang structure partially blocking the opening. The fill material is then reacted with a reactant to form a solid reaction product having a greater specific volume than the fill material. The overhang structure is thus converted into a reaction product structure blocking the opening. The reaction product (including the reaction product structure) is then desorbed, thereby exposing unreacted fill material at the bottom of the feature. The depositing and reacting steps may be repeated, with a final depositing step to fill the feature. Each sequence of depositing, reacting and desorbing reduces the aspect ratio of the feature.

摘要翻译： 描述了一种用于填充高纵横比特征的方法，其中以顺序执行相容的沉积和蚀刻步骤。 该特征形成为具有表面的基板中的开口; 填充材料沉积在特征的底部和基底的表面上; 在与特征相邻的表面上的沉积导致形成部分阻挡开口的突出结构。 然后将填充材料与反应物反应以形成具有比填充材料更大的比体积的固体反应产物。 因此，突出结构被转化成阻塞开口的反应产物结构。 然后将反应产物（包括反应产物结构）解吸，从而在特征底部暴露未反应的填充材料。 沉积和反应步骤可以重复，最终沉积步骤以填补该特征。 沉积，反应和解吸的每个顺序降低了特征的纵横比。

公开(公告)号：US6159870A

公开(公告)日：2000-12-12

申请号：US210411

申请日：1998-12-11

申请人： Ashima B. Chakravarti ,  Richard A. Conti ,  Frank V. Liucci ,  Darryl D. Restaino

发明人： Ashima B. Chakravarti ,  Richard A. Conti ,  Frank V. Liucci ,  Darryl D. Restaino

IPC分类号： H01L21/20 ,  H01L21/316 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/31604 ,  H01L21/31625 ,  H01L21/31629

摘要： A method of depositing a fluorinated borophosphosilicate glass (FBPSG) on a semiconductor device as either a final or interlayer dielectric film. Gaps having aspect ratios greater than 6:1 are filled with a substantially void-free FBPSG film at a temperature of about 480.degree. C. at sub-atmospheric pressures of about 200 Torr. Preferably, gaseous reactants used in the method comprise TEOS, FTES, TEPO and TEB with an ozone/oxygen mixture. Dopant concentrations of boron and phosphorus are sufficiently low such that surface crystallite defects and hygroscopicity are avoided. The as-deposited films at lower aspect ratio gaps are substantially void-free such that subsequent anneal of the film is not required. Films deposited into higher aspect ratio gaps are annealed at or below about 750.degree. C., well within the thermal budget for most DRAM, logic and merged logic-DRAM chips. The resultant FBPSG layer contains less than or equal to about 5.0 wt % boron, less than about 4.0 wt % phosphorus, and about 0.1 to 2.0 wt % fluorine.

摘要翻译： 在半导体器件上沉积氟化硼磷硅酸盐玻璃（FBPSG）作为最终或层间绝缘膜的方法。 纵横比大于6:1的间隙在约200托的亚大气压下，在约480℃的温度下填充基本上无空隙的FBPSG膜。 优选地，在该方法中使用的气态反应物包括具有臭氧/氧混合物的TEOS，FTES，TEPO和TEB。 硼和磷的掺杂浓度足够低，从而避免表面微晶缺陷和吸湿性。 较低纵横比间隙的沉积膜基本上无空隙，使得不需要膜的后续退火。 沉积在较高纵横比间隙中的膜在大约750℃或更低温度下退火，完全在大多数DRAM，逻辑和合并逻辑DRAM芯片的热预算内。 所得的FBPSG层含有小于或等于约5.0重量％的硼，小于约4.0重量％的磷和约0.1至2.0重量％的氟。

公开(公告)号：US6077786A

公开(公告)日：2000-06-20

申请号：US854011

申请日：1997-05-08

申请人： Ashima B. Chakravarti ,  Richard A. Conti ,  Donna R. Cote ,  Frank V. Liucci ,  Son V. Nguyen

发明人： Ashima B. Chakravarti ,  Richard A. Conti ,  Donna R. Cote ,  Frank V. Liucci ,  Son V. Nguyen

IPC分类号： H01L21/316 ,  H01L21/762 ,  H01L21/311

CPC分类号： H01L21/02274 ,  H01L21/02129 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02271 ,  H01L21/31625 ,  H01L21/76224

摘要： Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.

摘要翻译： 使用硅酸盐玻璃填充窄和/或高长宽比的间隙和沟槽在降低的温度下完成，并且通过在玻璃的热化学气相沉积中同时蚀刻玻璃而不进行回流，使得沉积速率将超过蚀刻速率相对较小 表面附近的净沉积速率随着沟槽或间隙的深度而增加。 通过在升高的温度下进行同时蚀刻和沉积工艺，但是在由先前执行的工艺形成的结构可以容忍的最大温度和热量预算范围内，将沉积的玻璃膜制成致密和稳定的。 氟可以以足够的浓度掺入到硅酸盐玻璃膜中作为掺杂剂以降低膜的介电常数。 也可以将磷和/或硼掺入到膜中，并且可以增强沟槽和间隙的无空隙填充。

公开(公告)号：US5540777A

公开(公告)日：1996-07-30

申请号：US541284

申请日：1995-10-12

申请人： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

发明人： Steven G. Barbee ,  Jonathan D. Chapple-Sokol ,  Richard A. Conti ,  Richard Hsiao ,  James A. O'Neill ,  Narayana V. Sarma ,  Donald L. Wilson ,  Justin W.-C. Wong ,  Steven P. Zuhoski

IPC分类号： C23C16/40 ,  C23C16/448 ,  C23C16/52 ,  H01L21/205 ,  H01L21/31 ,  H01L21/316 ,  C23C16/00

CPC分类号： C23C16/403 ,  C23C16/4481 ,  C23C16/52

摘要： A process and apparatus for Al.sub.2 O.sub.3 CVD on silicon wafers using aluminum tri-isopropoxide in a high-volume production environment is presented. The conditions required to use ATI in a production environment and provide maximum utilization of ATI are first of all delivery of ATI via direct evaporation. The ATI source bottle is pumped out (bypassing substrates) until propene and isopropanol signals are reduced to 1% of process pressure before start of aluminum oxide deposition. Either IR spectroscopy or mass spectrometry can be used to provide a control signal to the microprocessor controller. Heating the supplied tetramer to 120.degree. C. for two hours assures complete conversion to trimer. The ATI is stored at 90.degree. C. to minimize decomposition during idle periods and allow recovery of trimer upon return to 120.degree. C. for two hours. During periods of demand, the ATI is held at 120.degree. C. to minimize decomposition.

摘要翻译： 介绍了在大批量生产环境中使用三异丙氧基铝的硅晶片上Al2O3 CVD的工艺和装置。 在生产环境中使用ATI并提供ATI的最大利用率所需的条件首先通过直接蒸发传送ATI。 在开始氧化铝沉积之前，将ATI源瓶泵出（旁路基板），直到丙烯和异丙醇信号降低到过程压力的1％。 可以使用红外光谱或质谱法向微处理器控制器提供控制信号。 将供应的四聚体加热至120℃保持两小时，确保完全转化为三聚体。 将ATI储存在90℃以使空闲期间的分解最小化，并允许在回到120℃回收三聚体两小时。 在需求期间，ATI保持在120℃以最小化分解。