公开(公告)号：US06864752B2

公开(公告)日：2005-03-08

申请号：US10444022

申请日：2003-05-22

Applicant: Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

Inventor： Mario Caresosa ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03L7/099 ,  H03L7/18 ,  H04J3/04 ,  H04J3/06 ,  H04Q11/04

CPC classification number: H04J3/0685 ,  H03L7/099 ,  H03L7/0998 ,  H03L7/18 ,  H04J3/04 ,  H04J3/047 ,  H04J2203/0089

Abstract: A phase lock loop with multiple divider paths is presented herein. The phase lock loop can be used to provide a wide range of frequencies. The phase lock loop can also be used as a portion of a clock multiplier unit or a clock data and recovery unit.

公开(公告)号：US06760394B1

公开(公告)日：2004-07-06

申请号：US09632665

申请日：2000-08-07

Applicant: Jun Cao ,  Afshin Momtaz

Inventor： Jun Cao ,  Afshin Momtaz

IPC: H03D324

CPC classification number: H03L7/10 ,  H03L7/095 ,  Y10S331/02

Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

Abstract translation: 用于提高锁相环的精度和效率的方法和电路。 更具体地，本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置，以便提高锁相环的精度和效率。 在本发明的一个实施例中，使用两个计数器来检查VCO信号和外部基准或输入信号之间的频率差。 提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。 一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。 另外，使用数据存在信号来控制锁相模式和锁频模式之间的转换，以最小化潜在的数据丢失。

公开(公告)号：US06748041B1

公开(公告)日：2004-06-08

申请号：US10318586

申请日：2002-12-13

Applicant: Germain Gutierrez ,  Afshin Momtaz

Inventor： Germain Gutierrez ,  Afshin Momtaz

IPC: H03D324

CPC classification number: H03L7/107 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/099 ,  H03L7/18

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract translation: 各种电路技术在控制环路中采用跨导（gm）单元来实现诸如锁相环和延迟锁定环路之类的电路，这些电路能够以更高的频率工作，具有改进的精度和噪声性能。 gm单元被设计为在具有非常小的摆动和更渐进的过渡边缘的模拟输入信号上操作。 这些特征允许实现高频电路和系统，包括例如用于光纤通道的收发器，盘驱动器电子等。

公开(公告)号：US08964923B2

公开(公告)日：2015-02-24

申请号：US13168861

申请日：2011-06-24

Applicant: Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

Inventor： Anand Jitendra Vasani ,  Jun Cao ,  Afshin Momtaz

IPC: H04L25/00 ,  H04L7/00 ,  H03L7/081 ,  H04L7/033

CPC classification number: H04L7/0079 ,  H03L7/0812 ,  H04L7/033

Abstract: Provided is a low latency high bandwidth clock and data recovery (CDR) system. For example, there is a low latency high bandwidth CDR system including a demultiplexer configured to convert a high frequency input datastream to a low frequency output datastream according to a first latency and a phase error processor at least partially embedded into the demultiplexer and configured to determine a datastream phase error of the high frequency input datastream according to a second latency. The embedded phase error processor allows a portion of a total latency of the CDR system due to the demultiplexer and the phase error processor to be less than a sum of the first and second latencies.

Abstract translation: 提供了低延迟高带宽时钟和数据恢复（CDR）系统。 例如，存在低延迟高带宽CDR系统，其包括解复用器，其被配置为根据第一等待时间将高频输入数据流转换为低频输出数据流，并且相位误差处理器至少部分地被嵌入到解复用器中并且被配置为确定 根据第二等待时间，高频输入数据流的数据流相位误差。 嵌入式相位误差处理器允许由于解复用器和相位误差处理器而导致的CDR系统的总等待时间的一部分小于第一和第二延迟的和。

公开(公告)号：US08913706B2

公开(公告)日：2014-12-16

申请号：US12860596

申请日：2010-08-20

Applicant: Jun Cao ,  Afshin Momtaz ,  Chung-Jue Chen ,  Kang Xiao ,  Vivek Telang ,  Ali Ghiasi

Inventor： Jun Cao ,  Afshin Momtaz ,  Chung-Jue Chen ,  Kang Xiao ,  Vivek Telang ,  Ali Ghiasi

IPC: H03D3/24

CPC classification number: H03L7/18

Abstract: A circuit for producing one of a plurality of output clock frequencies from a single, constant input reference clock frequency. The circuit comprises a reference clock system and a phase lock loop. The reference clock system includes a bypass path, a divider path including a first integer divider, and a multiplexer. A divisor of the first integer divider is based on a selected communications protocol of a group of possible communications protocols. The multiplexer is configured to route the bypass path or the divider path based on the selected communications protocol. The phase lock loop includes a voltage controlled oscillator and a feedback path. The feedback path includes a second integer divider. A divisor of the second integer divider is based on the selected communications protocol. The reference clock system is configured to receive a constant reference clock frequency. The voltage controlled oscillator is configured to produce one of a plurality of output clock frequencies corresponding to the selected communications protocol. The selected output clock frequency is produced based on at least one of the routing of the multiplexer, the divisor of the first integer divider, and the divisor of the second integer divider.

Abstract translation: 一种用于从单个恒定输入参考时钟频率产生多个输出时钟频率之一的电路。 该电路包括参考时钟系统和锁相环。 参考时钟系统包括旁路路径，包括第一整数除法器的分频器路径和多路复用器。 第一整数分频器的除数基于一组可能的通信协议的所选通信协议。 多路复用器被配置为基于所选择的通信协议来路由旁路路径或分路器路径。 锁相环包括压控振荡器和反馈路径。 反馈路径包括第二整数分频器。 第二整数分频器的除数基于所选择的通信协议。 参考时钟系统被配​​置为接收恒定的参考时钟频率。 压控振荡器被配置为产生与所选择的通信协议相对应的多个输出时钟频率中的一个。 所选择的输出时钟频率基于多路复用器的路由，第一整数除法器的除数和第二整数除法器的除数中的至少一个来产生。

公开(公告)号：US08442159B2

公开(公告)日：2013-05-14

申请号：US12883842

申请日：2010-09-16

Applicant: Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

Inventor： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC: H04L27/06 ,  H03D1/00

CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

公开(公告)号：US08369453B2

公开(公告)日：2013-02-05

申请号：US12314051

申请日：2008-12-03

Applicant: Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

Inventor： Namik Kemal Kocaman ,  Afshin Momtaz ,  Velu Chellam Pillai ,  Vivek Telang ,  Sundararajan Chidambara ,  Magesh Valliappan

IPC: H03K9/00

CPC classification number: H04B17/21 ,  H03F3/195 ,  H03F2200/375 ,  H03F2200/405 ,  H04L25/03019 ,  H04L27/08

Abstract: An apparatus and method is disclosed to compensate for one or more offsets in a communications signal. A communications receiver may carry out an offset adjustment algorithm to compensate for the one or more offsets. An initial search procedure determines one or more signal metric maps for one or more selected offset adjustment corrections from the one or more offset adjustment corrections. The offset adjustment algorithm determines one or more optimal points for one or more selected offset adjustment correction based upon the one or more signal maps. The adaptive offset algorithm adjusts each of the one or more selected offset adjustment corrections to their respective optimal points and/or each of one or more non-selected offset adjustment corrections to a corresponding one of a plurality of possible offset corrections to provide one or more adjusted offset adjustment corrections. A tracking mode procedure optimizes the one or more adjusted offset adjustment corrections.

公开(公告)号：US20120313714A1

公开(公告)日：2012-12-13

申请号：US13158075

申请日：2011-06-10

Applicant: Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

Inventor： Mahyar Kargar ,  Siavash Fallahi ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03L7/00

CPC classification number: H03L7/0807 ,  H03L7/00 ,  H03L7/087 ,  H03L7/091 ,  H03L7/0991 ,  H03L7/113 ,  H03L2207/06 ,  H04L7/0004 ,  H04L7/033

Abstract: Embodiments for reference-less voltage controlled oscillator (VCO) calibration are provided. Embodiments include a VCO calibration module which uses one or more signals from a frequency detector to automatically select a proper VCO band and bring the VCO clock frequency close enough to the data rate. The VCO calibration module uses a calibration code to calibrate the VCO. In embodiments, the calibration code is determined using a frequency search scheme, which includes a discovery phase to determine the proper VCO band, and a binary search phase and a monitoring phase to select the calibration code that brings the VCO clock frequency closest to the data rate.

Abstract translation: 提供了无参考压控振荡器（VCO）校准的实施例。 实施例包括VCO校准模块，其使用来自频率检测器的一个或多个信号来自动选择适当的VCO频带并使VCO时钟频率接近于数据速率。 VCO校准模块使用校准代码校准VCO。 在实施例中，使用频率搜索方案来确定校准码，该频率搜索方案包括确定适当的VCO频带的发现阶段以及二进制搜索阶段和监视阶段，以选择使VCO时钟频率最接近数据的校准码 率。

公开(公告)号：US20110291757A1

公开(公告)日：2011-12-01

申请号：US13207887

申请日：2011-08-11

Applicant: Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

Inventor： Afshin Momtaz ,  Namik Kocaman ,  Bharath Raghavan

IPC: H03G3/20

CPC classification number: H03F3/45475 ,  H03F3/45183 ,  H03F2203/45686

Abstract: According to one general aspect, a distributed threshold adjuster (DTA) may be interspersed between stages of a multistage amplifier to adjust the DC voltage of an input signal. The DTA may include an input signal terminal configured to receive the input signal. The DTA may also include a plurality of current sources configured to produce an adjustment current signal whose amperage is configured to be increased or decreased by fixed steps in order to adjust the DC voltage of the input signal. The DTA may include a control unit configured to selectively turn on or off the individual current sources of the plurality of current sources to select the amperage of the adjustment current signal. The DTA may further include an output terminal configured to produce an output signal, comprising a combination of the input signal and the adjustment current signal, to a stage of a multistage amplifier.

Abstract translation: 根据一个一般方面，分布式阈值调节器（DTA）可以分散在多级放大器的级之间，以调节输入信号的直流电压。 DTA可以包括被配置为接收输入信号的输入信号端子。 DTA还可以包括多个电流源，其被配置为产生调节电流信号，其安培数被配置为通过固定步长增加或减小，以便调节输入信号的直流电压。 DTA可以包括控制单元，其被配置为选择性地打开或关闭多个电流源的各个电流源，以选择调节电流信号的电流强度。 DTA还可以包括输出端子，其被配置为产生包括输入信号和调整电流信号的组合的输出信号到多级放大器的级。

公开(公告)号：US20110235696A1

公开(公告)日：2011-09-29

申请号：US13152551

申请日：2011-06-03

Applicant: Afshin Momtaz

Inventor： Afshin Momtaz

IPC: H03H7/30

CPC classification number: H04L25/03057 ,  H04L2025/0349 ,  H04L2025/03617

Abstract: An equalizer that compensates for non-linear effects resulting from a transmitter, a receiver, and/or a communication channel in a communication system. A non-linear decision feedback equalizer compensates for the non-linear effects impressed onto a received symbol by selecting between equalization coefficients based upon a previous received symbol. The received symbol may be represented in form of logic signals based on the binary number system. When the previous received symbol is a binary zero, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary zero to compensate for the non-linear effects impressed onto the received symbol. When the previous received symbol is a binary one, the non-linear decision feedback equalizer selects an equalization coefficient corresponding to binary one to compensate for the non-linear effects impressed onto the received symbol.

Abstract translation: 一种均衡器，其补偿由通信系统中的发射机，接收机和/或通信信道产生的非线性效应。 非线性判决反馈均衡器通过基于先前接收到的符号在均衡系数之间进行选择来补偿对接收到的符号施加的非线性效应。 所接收的符号可以以基于二进制数系统的逻辑信号的形式表示。 当前一个接收到的符号是二进制零时，非线性判决反馈均衡器选择对应于二进制零的均衡系数来补偿被加载到接收符号上的非线性效应。 当先前接收到的符号是二进制符号时，非线性判决反馈均衡器选择对应于二进制符号的均衡系数来补偿被加载到接收符号上的非线性效应。