公开(公告)号：US5450605A

公开(公告)日：1995-09-12

申请号：US10360

申请日：1993-01-28

Applicant: Edward Grochowski ,  Kenneth Shoemaker ,  Uri Weiser ,  Doron Orenstein

Inventor： Edward Grochowski ,  Kenneth Shoemaker ,  Uri Weiser ,  Doron Orenstein

IPC: G06F9/32 ,  G06F9/30 ,  G06F9/38 ,  G06F12/04 ,  G06F13/16

CPC classification number: G06F9/30152 ,  G06F9/3816 ,  G06F9/3885

Abstract: The specification discloses a method and apparatus for determining the length of variable-length instructions that appear sequentially in an instruction stream without differentiation. The apparatus may be used to facilitate parallel processing of such variable-length instructions by a computer system. The apparatus includes: a circuit for providing a boundary marker for each instruction to indicate a boundary between that instruction and another instruction in the instruction stream, a circuit for processing instructions in sequence, a circuit for determining an actual boundary of a first instruction as it is processed, a circuit for comparing the boundary marker and the actual boundary of the first instruction to determine whether they match, a circuit for updating the boundary marker of the first instruction to the actual boundary of the first instruction when the boundary value and the actual boundary of the first instruction do not match, and a circuit for indicating a boundary between the first instruction and a next instruction from the stream of instructions based on the boundary marker of the first instruction.

Abstract translation: 本说明书公开了一种用于确定在不区分的指令流中顺序出现的可变长度指令的长度的方法和装置。 该装置可以用于促进计算机系统对这种可变长度指令的并行处理。 该装置包括：用于为每个指令提供边界标记以指示该指令与指令流中的另一指令之间的边界的电路，用于依次处理指令的电路，用于确定第一指令的实际边界的电路 处理的电路，用于比较第一指令的边界标记和实际边界以确定它们是否匹配的电路，用于当边界值和实际值与第一指令的边界标记更新为第一指令的实际边界的电路 第一指令的边界不匹配，以及用于基于第一指令的边界标记指示来自指令流的第一指令和下一指令之间的边界的电路。

公开(公告)号：US20130117531A1

公开(公告)日：2013-05-09

申请号：US13722485

申请日：2012-12-20

Applicant: Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

Inventor： Edward Grochowski ,  Julio Gago ,  Roger Gramunt ,  Roger Espasa ,  Rolf Kassa

IPC: G06F12/10

CPC classification number: G06F12/1009 ,  G06F12/0864 ,  G06F12/1027 ,  G06F12/109 ,  G06F12/145 ,  G06F2212/152 ,  G06F2212/6032 ,  G06F2212/652 ,  G06F2212/657 ,  G06F2212/68

Abstract: A method, system, and apparatus may initialize a fixed plurality of page table entries for a fixed plurality of pages in memory, each page having a first size, wherein a linear address for each page table entry corresponds to a physical address and the fixed plurality of pages are aligned. A bit in each of the page table entries for the aligned pages may be set to indicate whether or not the fixed plurality of pages is to be treated as one combined page having a second page size larger than the first page size. Other embodiments are described and claimed.

公开(公告)号：US07622961B2

公开(公告)日：2009-11-24

申请号：US11234548

申请日：2005-09-23

Applicant: Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

Inventor： Edward Grochowski ,  Chris Wilkerson ,  Shih-Lien L. Lu ,  Murali Annavaram

IPC: H03K5/19

CPC classification number: G01R31/31922 ,  G01R31/31726 ,  H03K5/1534 ,  H04L7/0083 ,  H04L7/033

Abstract: Two latches store the state of a data signal at a transition of a clock signal. Comparison logic compares the outputs of the two latches and produces a signal to indicate whether the outputs are equal or unequal. Systems using the latches and comparison logic are described and claimed.

Abstract translation: 两个锁存器在时钟信号的转变时存储数据信号的状态。 比较逻辑比较两个锁存器的输出，并产生一个信号以指示输出是相等还是不相等。 描述和要求保护使用锁存器和比较逻辑的系统。

公开(公告)号：US07437581B2

公开(公告)日：2008-10-14

申请号：US10952627

申请日：2004-09-28

Applicant: Edward Grochowski ,  John Shen ,  Hong Wang ,  Doron Orenstein ,  Gad S Sheaffer ,  Ronny Ronen ,  Murali M. Annavaram

Inventor： Edward Grochowski ,  John Shen ,  Hong Wang ,  Doron Orenstein ,  Gad S Sheaffer ,  Ronny Ronen ,  Murali M. Annavaram

IPC: G06F1/32 ,  G06F9/46

CPC classification number: G06F9/3851 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/329 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/3897 ,  Y02D10/16 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for changing the configuration of a multi-core processor is disclosed. In one embodiment, a throttle module (or throttle logic) may determine the amount of parallelism present in the currently-executing program, and change the execution of the threads of that program on the various cores. If the amount of parallelism is high, then the processor may be configured to run a larger amount of threads on cores configured to consume less power. If the amount of parallelism is low, then the processor may be configured to run a smaller amount of threads on cores configured for greater scalar performance.

Abstract translation: 公开了一种用于改变多核处理器的配置的方法和装置。 在一个实施例中，节气门模块（或节气门逻辑）可以确定当前执行的程序中存在的并行度量，并且改变该程序在各种核心上的线程的执行。 如果并行量高，则处理器可以被配置为在被配置为消耗较少功率的核上运行更大量的线程。 如果并行量较低，则处理器可能被配置为在配置为更高标量性能的核心上运行较少量的线程。

公开(公告)号：US20070271421A1

公开(公告)日：2007-11-22

申请号：US11435701

申请日：2006-05-17

Applicant: Nam Sung Kim ,  Shih-Lien L. Lu ,  Chris Wilkerson ,  Edward Grochowski

Inventor： Nam Sung Kim ,  Shih-Lien L. Lu ,  Chris Wilkerson ,  Edward Grochowski

IPC: G06F13/00

CPC classification number: G11C11/412

Abstract: Methods and apparatus to reduce aging effect on memory are described. In one embodiment, a modified version of data is stored in a portion of a storage unit during a first time period.

Abstract translation: 描述了减少老化对记忆效应的方法和装置。 在一个实施例中，数据的修改版本在第一时间段期间存储在存储单元的一部分中。

公开(公告)号：US20070225959A1

公开(公告)日：2007-09-27

申请号：US11804860

申请日：2007-05-21

Applicant: Edward Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David Ayers

Inventor： Edward Grochowski ,  David Sager ,  Vivek Tiwari ,  Ian Young ,  David Ayers

IPC: G06F17/50

CPC classification number: G06F1/3296 ,  G06F1/26 ,  G06F1/3203 ,  G06F17/5036 ,  G06F2217/78 ,  Y02D10/172

Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

公开(公告)号：US20050081017A1

公开(公告)日：2005-04-14

申请号：US10685654

申请日：2003-10-14

Applicant: Jeffrey Rupley ,  Edward Brekelbaum ,  Edward Grochowski ,  Bryan Black

Inventor： Jeffrey Rupley ,  Edward Brekelbaum ,  Edward Grochowski ,  Bryan Black

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3836 ,  G06F9/384

Abstract: Disclosed are an apparatus, system, and method for implementing predicated instructions using micro-operations. A micro-code engine receives an instruction, decomposes the instruction, and generates a plurality of micro-operations to implement the instruction. Each of the decomposed micro-operations indicates a single destination register. For predicated instructions, the decomposed micro-operations include “conditional move” micro-operations to select between two potential output values. Except in the case that one of the potential output values is a constant, the decomposed micro-operations for a predicated instruction also include an append instruction that saves the incoming value of a destination register in a temporary variable. For at least one embodiment, the qualifying predicate for a predicated instruction is appended to the incoming value stored in the temporary register.

Abstract translation: 公开了一种用于使用微操作来实现预定指令的装置，系统和方法。 微码引擎接收指令，分解指令，并产生多个微操作来实现该指令。 每个分解的微操作指示单个目的地寄存器。 对于预测指令，分解的微操作包括在两个潜在输出值之间选择的“条件移动”微操作。 除了在一个潜在输出值是常数的情况下，用于预测指令的分解的微操作还包括将目的地寄存器的输入值保存在临时变量中的附加指令。 对于至少一个实施例，用于预测指令的限定谓词附加到存储在临时寄存器中的输入值。

公开(公告)号：US06839814B2

公开(公告)日：2005-01-04

申请号：US10726492

申请日：2003-12-04

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US06675266B2

公开(公告)日：2004-01-06

申请号：US09750094

申请日：2000-12-29

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F1200

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory circuit includes a plurality of memory bit circuits coupled together to form an n-bit memory cell, and a valid bit circuit coupled to the n-bit memory cell, the valid bit circuit being configured to be accessed simultaneously with the plurality of memory bit circuits.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并且被设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的实施例，标签阵列存储电路包括耦合在一起以形成n位存储单元的多个存储器位电路和耦合到n位存储单元的有效位电路，有效位 电路被配置为与多个存储器位电路同时访问。

公开(公告)号：US6035389A

公开(公告)日：2000-03-07

申请号：US132043

申请日：1998-08-11

Applicant: Edward Grochowski ,  Hans Mulder ,  Derrick C. Lin

Inventor： Edward Grochowski ,  Hans Mulder ,  Derrick C. Lin

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3838 ,  G06F9/3863

Abstract: An apparatus includes a clock to produce pulses and an electronic hardware structure having a plurality of rows and one or more ports. Each row is adapted to record a separate latency vector written through one of the ports. The latency vector recorded therein is responsive to the clock. A method of dispatching instructions in a processor includes updating a plurality of expected latencies to a portion of rows of a register latency table, and decreasing the expected latencies remaining in other of the rows in response to a clock pulse. The rows of the portion correspond to particular registers.

Abstract translation: 一种装置包括产生脉冲的时钟和具有多个行和一个或多个端口的电子硬件结构。 每行适于记录通过其中一个端口写入的单独的延迟矢量。 其中记录的等待时间向量响应时钟。 在处理器中调度指令的方法包括将多个预期延迟更新为寄存器延迟表的行的一部分，并且响应于时钟脉冲减少其余行中剩余的预期延迟。 该部分的行对应于特定寄存器。