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公开(公告)号:US12063865B2
公开(公告)日:2024-08-13
申请号:US16989155
申请日:2020-08-10
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev Aggarwal , Sarin A. Deshpande , Kerry Joseph Nagel
Abstract: A method of fabricating a magnetoresistive bit from a magnetoresistive stack includes etching through a first portion of the magnetoresistive stack using a first etch process to form one or more sidewalls. At least a portion of the sidewalls includes redeposited material after the etching. The method also includes modifying at least a portion of the redeposited material on the sidewalls, and etching through a second portion of the magnetoresistive stack after the modifying step. The magnetoresistive stack may include a first magnetic region, an intermediate region disposed over the first magnetic region, and a second magnetic region disposed over the intermediate region.
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公开(公告)号:US12022738B2
公开(公告)日:2024-06-25
申请号:US17270151
申请日:2019-08-22
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev Aggarwal , Sarin Deshpande , Kerry Nagel , Santosh Karre
CPC classification number: H10N50/01 , H10N50/80 , H01F10/3254 , H01F10/3272 , H10B61/00
Abstract: Fabrication of a magnetic memory element, including a via (125) in an interlevel dielectric layer (120), providing an electrical connection between an underlying metal region (110) and a magnetoresistive stack device, such as a magnetic tunnel junction (150), involves forming a transition metal layer (130) in the via by atomic layer deposition. The via optionally includes a tantalum-rich layer (140) above, and/or a cap layer (115) below, the transition metal layer, and may have a diameter less than or equal than a diameter of the magnetoresistive stack device.
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公开(公告)号:US11757451B2
公开(公告)日:2023-09-12
申请号:US17652905
申请日:2022-02-28
Applicant: Everspin Technologies, Inc.
Inventor: Dimitri Houssameddine , Syed M. Alam , Sanjeev Aggarwal
IPC: H03K19/1776 , G11C11/16 , G11C13/00 , H03K19/17784 , H03K19/17724 , G06F21/78
CPC classification number: H03K19/1776 , G11C11/1675 , G11C13/0069 , H03K19/17724 , H03K19/17784 , G06F21/78
Abstract: The present disclosure is drawn to, among other things, a configuration bit including at least four resistive elements and a voltage amplifier. At least two first resistive elements may be electrically connected in series via a first electrode and at least two second resistive elements may be electrically connected in series via a second electrode. The at least two first resistive elements may be electrically connected in parallel to the at least two second resistive elements via a third electrode and a fourth electrode. The first electrode and the second electrode may be electrically connected to a voltage supply. The third electrode and the fourth electrode may be electrically connected to an input of the voltage amplifier.
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公开(公告)号:US11690229B2
公开(公告)日:2023-06-27
申请号:US17131926
申请日:2020-12-23
Applicant: Everspin Technologies, Inc.
Inventor: Jijun Sun , Sanjeev Aggarwal , Han-Jong Chia , Jon M. Slaughter , Renu Whig
CPC classification number: H01L27/222 , G11B5/3909 , G11C11/1673 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12
Abstract: A magnetoresistive stack/structure and method of manufacturing same comprising wherein the stack/structure includes a seed region, a fixed magnetic region disposed on and in contact with the seed region, a dielectric layer(s) disposed on the fixed magnetic region and a free magnetic region disposed on the dielectric layer(s). In one embodiment, the seed region comprises an alloy including nickel and chromium having (i) a thickness greater than or equal to 40 Angstroms (+/−10%) and less than or equal to 60 Angstroms (+/−10%), and (ii) a material composition or content of chromium within a range of 25-60 atomic percent (+/−10%) or 30-50 atomic percent (+/−10%).
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公开(公告)号:US11482570B2
公开(公告)日:2022-10-25
申请号:US17134865
申请日:2020-12-28
Applicant: Everspin Technologies, Inc.
Inventor: Kerry Joseph Nagel , Sanjeev Aggarwal , Thomas Andre , Sarin A. Deshpande
Abstract: Magnetoresistive device architectures and methods for manufacturing are presented that facilitate integration of process steps associated with forming such devices into standard process flows used for surrounding logic/circuitry. In some embodiments, the magnetoresistive device structures are designed such that the devices are able to fit within the vertical dimensions of the integrated circuit associated with a single metal layer and a single layer of interlayer dielectric material. Integrating the processing for the magnetoresistive devices can include using the same standard interlayer dielectric material as used in the surrounding circuits on the integrated circuit as well as using standard vias to interconnect to at least one of the electrodes of the magnetoresistive devices.
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公开(公告)号:US11031546B2
公开(公告)日:2021-06-08
申请号:US16194523
申请日:2018-11-19
Applicant: Everspin Technologies, Inc.
Inventor: Kerry Joseph Nagel , Kenneth H. Smith , Moazzem Hossain , Sanjeev Aggarwal
IPC: H01L21/3213 , H01L27/22 , H01L43/12 , H01L43/08 , H01L21/768 , H01L21/285 , H01L43/02
Abstract: A method of manufacturing one or more interconnects to magnetoresistive structure comprising (i) depositing a first conductive material in a via; (2) etching the first conductive material wherein, after etching the first conductive material a portion of the first conductive material remains in the via, (3) partially filling the via by depositing a second conductive material in the via and directly on the first conductive material in the via; (4) depositing a first electrode material in the via and directly on the second conductive material in the via; (5) polishing a first surface of the first electrode material wherein, after polishing, the first electrode material is (i) on the second conductive material in the via and (ii) over the portion of the first conductive material remaining in the via; and (6) forming a magnetoresistive structure over the first electrode material.
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公开(公告)号:US11004899B2
公开(公告)日:2021-05-11
申请号:US16395396
申请日:2019-04-26
Applicant: Everspin Technologies, Inc.
Inventor: Sanjeev Aggarwal , Jijun Sun
Abstract: A magnetoresistive device may include a first ferromagnetic region, a second ferromagnetic region, and an intermediate region positioned between the first ferromagnetic region and the second ferromagnetic region. The intermediate region may be formed of a dielectric material and comprise at least two different metal oxides.
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公开(公告)号:US10297747B2
公开(公告)日:2019-05-21
申请号:US15958444
申请日:2018-04-20
Applicant: Everspin Technologies, Inc.
Inventor: Sarin A. Deshpande , Sanjeev Aggarwal , Moazzem Hossain
Abstract: The present disclosure is drawn to, among other things, a method of fabricating an integrated circuit device having a magnetoresistive device. In some aspects, the method includes forming the magnetoresistive device on a first contact of a substrate, wherein the magnetoresistive device includes a fixed magnetic region and a free magnetic region separated by an intermediate region; depositing a first dielectric material over the magnetoresistive device; depositing a second dielectric material over the first dielectric material; polishing a surface of the second dielectric material; forming a first cavity through the polished surface of the second dielectric material to expose a surface of the magnetoresistive device; and depositing an electrically conductive material in the first cavity to form a via.
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公开(公告)号:US09893274B2
公开(公告)日:2018-02-13
申请号:US15388650
申请日:2016-12-22
Applicant: EVERSPIN TECHNOLOGIES, INC.
Inventor: Renu Whig , Phillip Mather , Kenneth Smith , Sanjeev Aggarwal , Jon Slaughter , Nicholas Rizzo
CPC classification number: H01L43/12 , B82Y25/00 , G01R33/0052 , G01R33/09 , G01R33/093 , G01R33/098 , H01L27/22 , H01L43/02 , H01L43/08
Abstract: A semiconductor process integrates three bridge circuits, each include magnetoresistive sensors coupled as a Wheatstone bridge on a single chip to sense a magnetic field in three orthogonal directions. The process includes various deposition and etch steps forming the magnetoresistive sensors and a plurality of flux guides on one of the three bridge circuits for transferring a “Z” axis magnetic field onto sensors orientated in the XY plane.
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公开(公告)号:US09865804B2
公开(公告)日:2018-01-09
申请号:US15630377
申请日:2017-06-22
Applicant: Everspin Technologies, Inc.
Inventor: Sarin A. Deshpande , Sanjeev Aggarwal , Kerry Joseph Nagel
CPC classification number: H01L43/12 , G11B5/84 , G11C11/161 , H01L27/222 , H01L43/02 , H01L43/08
Abstract: A magnetoresistive-based device and method of manufacturing a magnetoresistive-based device using one or more hard masks. The process of manufacture, in one embodiment, includes patterning a mask over a selected portion of the third layer of ferromagnetic material, wherein the mask is a metal hard mask. Thereafter, etching through the third layer of ferromagnetic material to provide sidewalls of the second synthetic antiferromagnetic structure, through the second tunnel barrier layer to form a second tunnel barrier and provide sidewalls thereof and the second layer of ferromagnetic material to provide sidewalls thereof. Thereafter, etching, through the first tunnel barrier layer to form a first tunnel barrier to provide sidewalls thereof and etching the first layer of ferromagnetic material to provide sidewalls thereof. The process may then include oxidizing the sidewalls of (i) the first tunnel barrier and (ii) the first layer of ferromagnetic material. Thereafter, the metal hard mask may be connected to an electrical conductor.
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