公开(公告)号：US20100244206A1

公开(公告)日：2010-09-30

申请号：US12414794

申请日：2009-03-31

申请人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

发明人： Huiming Bu ,  Michael P. Chudzik ,  Wei He ,  Rashmi Jha ,  Young-Hee Kim ,  Siddarth A. Krishnan ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle

IPC分类号： H01L23/00 ,  H01L21/314

CPC分类号： H01L21/28202 ,  H01L21/28176 ,  H01L21/28185 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a device includes providing a substrate, forming an interfacial layer on the substrate, depositing a high-k dielectric layer on the interfacial layer, depositing an oxygen scavenging layer on the high-k dielectric layer and performing an anneal. A high-k metal gate transistor includes a substrate, an interfacial layer on the substrate, a high-k dielectric layer on the interfacial layer and an oxygen scavenging layer on the high-k dielectric layer.

摘要翻译： 形成器件的方法包括提供衬底，在衬底上形成界面层，在界面层上沉积高k电介质层，在高k电介质层上沉积氧气清除层并执行退火。 高k金属栅极晶体管包括衬底，衬底上的界面层，界面层上的高k电介质层和高k电介质层上的氧清除层。

公开(公告)号：US20090298275A1

公开(公告)日：2009-12-03

申请号：US12539860

申请日：2009-08-12

申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

IPC分类号： H01L21/28

CPC分类号： H01L29/517 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

摘要翻译： 公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。 该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。 该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。 耗尽的侧壁层是非晶硅或多晶硅之一。 该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

公开(公告)号：US20090280631A1

公开(公告)日：2009-11-12

申请号：US12117769

申请日：2008-05-09

申请人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

发明人： Jeffrey P. Gambino ,  Michael P. Chudzik ,  Renee T. Mo

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/495 ,  H01L21/28079 ,  H01L21/82345 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention, in one embodiment provides a method of forming a semiconducting device including providing a substrate including a semiconducting surface, the substrate comprising a first device region and a second device region; forming a high-k dielectric layer atop the semiconducting surface of the substrate; forming a block mask atop the second device region of the substrate, wherein the first device region of the substrate is exposed; forming a first metal layer atop the high-k dielectric layer present in the first device region of the substrate; removing the block mask to expose a portion of the high-k dielectric layer in the first device region of the substrate; forming a second metal layer atop the portion of the high-k dielectric layer in the second device region and atop the first metal in the first device region of the substrate; and forming gate structures in the first and second device regions of the substrate.

摘要翻译： 本发明在一个实施例中提供了一种形成半导体器件的方法，包括提供包括半导体表面的衬底，该衬底包括第一器件区域和第二器件区域; 在衬底的半导体表面上方形成高k电介质层; 在所述衬底的所述第二器件区域的顶部形成掩模掩模，其中所述衬底的所述第一器件区域被暴露; 在存在于所述衬底的第一器件区域中的高k电介质层的顶部形成第一金属层; 去除所述块掩模以暴露所述衬底的所述第一器件区域中的所述高k电介质层的一部分; 在所述第二器件区域中的所述高k电介质层的所述部分的顶部上形成第二金属层，并且在所述衬底的所述第一器件区域中的所述第一金属顶上形成第二金属层; 以及在所述衬底的所述第一和第二器件区域中形成栅极结构。

公开(公告)号：US20090065817A1

公开(公告)日：2009-03-12

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L29/78

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在所述FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US07498271B1

公开(公告)日：2009-03-03

申请号：US12145035

申请日：2008-06-24

申请人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

发明人： Ricardo A. Donaton ,  Rashmi Jha ,  Siddarth A. Krishnan ,  Xi Li ,  Renee T. Mo ,  Naim Moumen ,  Wesley C. Natzle ,  Ravikumar Ramachandran ,  Richard S. Wise

IPC分类号： H01L21/31

CPC分类号： H01L21/31138 ,  H01L21/28202 ,  H01L21/31155 ,  H01L21/823828 ,  H01L21/823878 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

摘要翻译： 本发明在一个实施例中提供了一种形成栅极结构的方法，该栅极结构包括提供包括半导体器件区域的衬底，在半导体器件区域顶部存在的高k电介质材料以及高k电介质顶部的金属栅极导体 材料，在金属栅极导体顶上施加光致抗蚀剂层; 图案化光致抗蚀剂层以提供覆盖对应于栅极堆叠的金属栅极导体的一部分的蚀刻掩模; 蚀刻对蚀刻掩模有选择性的金属栅极导体和高k电介质材料; 并用基本上不含氧的氮气等离子体去除蚀刻掩模。

公开(公告)号：US20080203485A1

公开(公告)日：2008-08-28

申请号：US11680108

申请日：2007-02-28

申请人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

发明人： Michael P. Chudzik ,  Wei He ,  Renee T. Mo ,  Naim Moumen ,  Vijay Narayanan ,  Dae-gyu Park ,  Vamsi Paruchuri

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/78 ,  H01L29/7845

摘要： A gate structure for complementary metal oxide semiconductor (CMOS) devices includes a first gate stack having a first gate dielectric layer formed over a substrate, and a first metal layer formed over the first gate dielectric layer. A second gate stack includes a second gate dielectric layer formed over the substrate and a second metal layer formed over the second gate dielectric layer. The first metal layer is formed in manner so as to impart a tensile stress on the substrate, and the second metal layer is formed in a manner so as to impart a compressive stress on the substrate.

摘要翻译： 用于互补金属氧化物半导体（CMOS）器件的栅极结构包括具有形成在衬底上的第一栅极介电层的第一栅极堆叠和形成在第一栅极介电层上的第一金属层。 第二栅极堆叠包括形成在衬底上的第二栅极电介质层和形成在第二栅极介电层上的第二金属层。 第一金属层形成为在基板上施加拉伸应力，并且第二金属层以使得在基板上施加压应力的方式形成。

公开(公告)号：US09263276B2

公开(公告)日：2016-02-16

申请号：US12551292

申请日：2009-11-18

申请人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Renee T. Mo ,  Wesley C. Natzle ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66

CPC分类号： H01L21/28088 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A transistor is provided that includes a silicon layer with a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, an L shaped gate encapsulation layer disposed on sidewalls of the gate stack, and a spacer disposed above the horizontal portion of the gate encapsulation layer and adjacent to the vertical portion of the gate encapsulation layer. The gate stack has a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The gate encapsulation layer has a vertical portion covering the sidewalls of the first, second, and third layers of the gate stack and a horizontal portion covering a portion of the silicon layer that is adjacent to the gate stack.

公开(公告)号：US09059316B2

公开(公告)日：2015-06-16

申请号：US13397860

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L21/8238 ,  H01L21/768 ,  H01L21/84 ,  H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/32 ,  H01L29/165

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

摘要翻译： 虽然嵌入式硅锗合金和硅碳合金提供了许多有用的应用，特别是为了通过应力工程增强MOSFET的迁移率，在这些表面上形成合金化硅化物降低了器件性能。 本发明提供了在放置在半导体衬底上的这种硅合金表面上提供非合金硅化物的结构和方法。 这使得能够在具有嵌入式SiGe的迁移率增强的PFET和在同一半导体衬底上具有嵌入的Si：C的迁移率增强的NFET形成低电阻触点。 此外，本发明提供了在栅极电介质的电平之上的厚外延硅合金，特别是厚的外延Si：C合金的方法，以增加晶体管器件上的沟道上的应力。

公开(公告)号：US08878298B2

公开(公告)日：2014-11-04

申请号：US13346165

申请日：2012-01-09

申请人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

发明人： Josephine B. Chang ,  Leland Chang ,  Renee T. Mo ,  Vijay Narayanan ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7856 ,  H01L29/66795

摘要： Multiple threshold voltage (Vt) field-effect transistor (FET) devices and techniques for the fabrication thereof are provided. In one aspect, a FET device is provided including a source region; a drain region; at least one channel interconnecting the source and drain regions; and a gate, surrounding at least a portion of the channel, configured to have multiple threshold voltages due to the selective placement of at least one band edge metal throughout the gate.

摘要翻译： 提供了多阈值电压（Vt）场效应晶体管（FET）器件及其制造技术。 一方面，提供一种FET器件，其包括源极区域; 漏区; 将源极和漏极区互连的至少一个沟道; 以及围绕通道的至少一部分的栅极，其被配置为具有多个阈值电压，这是由于至少一个带边缘金属选择性地放置在整个栅极上。

公开(公告)号：US08816473B2

公开(公告)日：2014-08-26

申请号：US13440172

申请日：2012-04-05

申请人： Arvind Kumar ,  Anthony I-Chih Chou ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Arvind Kumar ,  Anthony I-Chih Chou ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L21/84 ,  H01L28/20 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.

摘要翻译： 公开了提供精密电阻元件的半导体结构和制造方法。 多晶硅嵌入在硅衬底中。 可以掺杂多晶硅以控制电阻。 实施例可以包括电阻器，eFuse和绝缘体上硅结构。 一些实施例可以包括非矩形横截面。