公开(公告)号：US10056457B2

公开(公告)日：2018-08-21

申请号：US15595717

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/745 ,  H01L29/739 ,  H01L29/74

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US10002920B1

公开(公告)日：2018-06-19

申请号：US15379214

申请日：2016-12-14

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US20170338314A1

公开(公告)日：2017-11-23

申请号：US15595643

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74 ,  H01L29/739

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20170243970A1

公开(公告)日：2017-08-24

申请号：US15052664

申请日：2016-02-24

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Ljubisa Dragoljub Stevanovic ,  Greg Thomas Dunne ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

公开(公告)号：US09735263B2

公开(公告)日：2017-08-15

申请号：US14787545

申请日：2013-11-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L27/088 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.

公开(公告)号：US09735237B2

公开(公告)日：2017-08-15

申请号：US14752446

申请日：2015-06-26

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/872 ,  H01L29/808

CPC classification number: H01L29/1608 ,  H01L29/0634 ,  H01L29/6606 ,  H01L29/8083 ,  H01L29/872

Abstract: The subject matter disclosed herein relates to silicon carbide (SiC) power devices and, more specifically, to active area designs for SiC super-junction (SJ) power devices. A SiC-SJ device includes an active area having one or more charge balance (CB) layers. Each CB layer includes a semiconductor layer having a first conductivity-type and a plurality of floating regions having a second conductivity-type disposed in a surface of the semiconductor layer. The plurality of floating regions and the semiconductor layer are both configured to substantially deplete to provide substantially equal amounts of charge from ionized dopants when a reverse bias is applied to the SiC-SJ device.

公开(公告)号：US20150115284A1

公开(公告)日：2015-04-30

申请号：US14396852

申请日：2013-05-15

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Kevin Sean Matocha ,  Richard Joseph Saia ,  Zachary Matthew Stum ,  Ljubisa Dragoljub Stevanovic ,  Kuna Venkat Satya Rama Kishore ,  James William Kretchmer

IPC: H01L29/36 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/0638 ,  H01L21/0465 ,  H01L29/0619 ,  H01L29/0646 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/6606 ,  H01L29/7395 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613

Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.

Abstract translation: 半导体器件包括：包含碳化硅的衬底; 设置在所述衬底上的漂移层，包括掺杂有第一掺杂剂和导电类型的漂移区; 以及掺杂有第二掺杂剂和导电类型的第二区域，其邻近漂移区并且靠近漂移层的表面。 所述半导体器件还包括与所述第二区相邻的连接终端延伸部，所述连接终端延伸部具有在掺杂有不同浓度的所述第二掺杂剂类型的第一和第二方向上分离的宽度和离散区域以及所述第二导电类型的功能形式的有效掺杂分布 这通常从主阻塞结的边缘减小。 宽度小于或等于一维耗尽宽度宽度的五倍的倍数，半导体器件的电荷容差大于1.0×1013 / cm2。

公开(公告)号：US20150008449A1

公开(公告)日：2015-01-08

申请号：US13934053

申请日：2013-07-02

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/22

CPC classification number: H01L29/1608 ,  H01L21/22 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/7827

Abstract: A semiconductor device includes a silicon carbide (SiC) drift layer disposed on a (0001) oriented SiC substrate. The SiC drift layer has a non-planar surface including a plurality of repeating features that are oriented parallel to a length of a channel of the semiconductor device. Further, the channel region is disposed in a particular crystallographic plane of the SiC drift layer.

Abstract translation: 半导体器件包括设置在（0001）取向的SiC衬底上的碳化硅（SiC）漂移层。 SiC漂移层具有包括平行于半导体器件的沟道的长度定向的多个重复特征的非平面表面。 此外，沟道区设置在SiC漂移层的特定结晶平面中。

公开(公告)号：US20140361315A1

公开(公告)日：2014-12-11

申请号：US14467754

申请日：2014-08-25

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Zachary Matthew Stum ,  Stephen Daley Arthur ,  Kevin Sean Matocha ,  Peter Almern Losee

IPC: H01L29/36 ,  H01L29/78 ,  H01L29/16

CPC classification number: H01L29/36 ,  H01L21/046 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7816 ,  H01L29/7827

Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.

Abstract translation: 根据一个实施例的半导体器件具有包括第一掺杂剂类型的第一区域，与第二掺杂剂类型的第一区域相邻的第二区域和沟道区域。 存在与具有第二掺杂剂类型的沟道区隔开的第三区域，其中第三区域基本上与第二区域重合。

公开(公告)号：US20210288180A1

公开(公告)日：2021-09-16

申请号：US17338337

申请日：2021-06-03

Applicant: General Electric Company

Inventor： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

Abstract: A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.